Go to the A-R-T Home Page

The RC7500 (PID-7500)

A Computer Workstation and Development Board for the ARM7500
View or Download PDF

Main Component list:

  1. CS750032 bit RISC Processor with Cache, CIRRUS
  2. MMU, and Write Buffer
  3. FPE
  4. Memory Controller
  5. Video Controller
  6. IO interface
  7. audio Output
  8. Keyboard/ Mouse/ Joystick

  9. SMC 37C665(2) Serial Ports with FIFO
  10. IO COMBO Bi-directional Parallel Port
  11. Floppy Controller
  12. (2) IDE interfaces

  13. SMC 91C92Ethernet Controller. 10Base-T only

  14. DRAM 256Kx8Bit by 4 SIMMs = 1 MByte
  15. 1Mx 8 Bit by 4 SIMMs = 4 MByte
  16. 4Mx 8 Bit by 4 SIMMs = 16 MByte

  17. 28/32 Pin EPROM4x27C256 = 128K Bytes
  18. 4x27C010 = 512K Bytes
Theory of Operation:

From the Schematic. -OR- Why did I do it this way?:

Page 1 CLOCK Generation and DRAM

The Board clocks are generated by a Chrontel CH9294 usually used for VGA cards. It provide 3 clocks, The first being the 14.318 Mhz 4x color burst frequency used on PC motherboards to generate the OSC signal used on the expansion slot.. The three 7500 clocks are usually connected to the MCLK output of the CH9294. This output is programmed by the jumpers JP1 through JP3 (See table in appendix a) to be nominally at 65MHz. This means that the processor cache clock will be 32.5 Mhz. The VCLK output of the CH9294 is programmed by an output register. This clock is normally used to provide a video clock for VGA and super VGA pixel rates and goes back to the VIDC section of the Next7500.

Standard 30 Pin SIMMs are used for the memory on this version of the board because they give flexibility in the main mamory capacity and because when the board was designed they were cheaper and more avialable than the 72 pin SIMMs. as I have waited for the layout and FaB to take place I have noted that the 72 Pin SIMMs have started to cross over the 30 pin SIMMs. Thus later versions of the board will use the newer part.

The PCF8583 was chosen for the real time clock chip because it is the standard chosen by Acorn and the ARM7500 has 2 pins dedicated for I2 C operation. The PCF8583 offers additional batery backed RAM, which can be used for saving system hardware data. The RC7500 board has room for a 3 Volt Lithium battery, but on the first versions do not have the battery loaded. a standard external PC motherboard battery can be used. The PCF8583 has a clock interrupt pin that is connected to the NEVENT1. The PAnis Button is connected to NEVENT2. Either of these two interrupts can wake up the ARM7500 from power down modes. Thus the RC7500 computer could be put into an lengthy sleep and awakened by the alarm clock. To really shake things up the on board reset button or front panel reset button can be depressed.

Page 2 ROM

The RC7500 is equipt with 4 ROM/ EPROM sockets. Since the ARM7500 can support both 16 and 32 bit memories as little as 64 Kilo-Bytes (2 x 27C256) or as much as 4 Mega-Bytes ( 4 x 27C080) of read only memory can be used. This means anything from a boot loader to a complete operating system with many utilities can be placed in ROM. addressing ofvarious types of ROM is provided by 5 jumpers (JP4 to JP8).

The ARM7500 generates the low going ROMOE signal which is connected to the ROM OE pins. When an external ROM emulator is hooked up to the Logic analyser port the on board ROM can be disable by pulling the DISaROM signal high.

Page 3 CLOCK Keyboard, Mouse and Joystick, etc.

The ARM7500 has two electrically identical keyboard ports that are assigned to Keyboard and PS/2 Mouse connectors. These are "AT" compatible bidirectional open drain serial ports. Dual diodes and capacitors are used for static protection and noise reduction. The bit rate on these pins are fairly slow so .001 uf caps do not affect the signals.

The ARM7500 has 4 single slope A/D converters. Each pin has of open drain transistor and an attached voltage comparator which controlls a 16 bit ripple counter. When the transistor is turned off, the voltage on the pin rises as current froma resistor connected to the +5 volt supply charges a capacitor connected to ground. When the voltage rises to the comparator threshold (at 2 volts) an interrupt is signalled and the 16 bit ripple counter stops. The counter is run from the IOCLK divided by 32 (nominally 2 Mhz) which allows for a 32,768 usec maximum time period. Normally the 100 KOhm Joystick pots provide the resistor to +5 Volts. In a PC they are routed to a SE555 timer circuit which is timed by the CPU with interrupts off for as long a several milliseconds. The self timed ARM7500 a/D circuits prevent having to turn the CPU interrupts of for such a long period.

I made some effort to make these unique inputs more versatile than joystick only ports. If an external rising signal were substituted for the resistor and capacitor formed slope, the pins could be used for simple timers. an example of this type of input could be Polaroid Sonars used in Robots. The distance to nearby objects could then be measured for 4 inputs simultaneously (up to 16 feet at 2 milliseconds per foot). To allow for use as a timer the capacitors are switched out and pull-up resistors are switched in to each A/D input with 74HC4066 analog switches.

In the Etc, department is and a 74HC377 used to control front panel LEDs, the audio volume control and the video frequency select on the CH9294. The 4 joystick buttons are sensed with a aHC21 (4 input and gate) and the 74HC541 latch. This part also is used to sense which serial port is interrupting and the state of the front panel TURBO switch.

Page 4 CDROM audio and VGA Video outputs.

The RC7500 does have its own audio D/a circuitry, but it is an 8 bit companding type in which there are 8 cords of 16 steps each with one sign bit. The ARM sound circuitry allows for 8 mono channels that are stearable in 8 steps from left to right. although companding codecs are good enough for voice quality they are definitely not "HiFi" (pretty lousy to me!). also handling 8 channels requires a great deal of processor power as 8 channels of 8 bits require more bandwidth than a 32bit sterio channel. The 8 bit sound samples are converted to 16 bits with a "antilog" table before they can be scaled or added and then recompressed with a "log" table. Compare this with simple linear scaling and addition. To avoid this programming mess I opted for an inexpensive CD D/a ( Philips TDa1543) found in many CD players. The designers of the ARM allowed for connecting to this very part.

The ARM7500 supports direct drive RGB outputs into doubly terminated 75 ohm lines. I added protection diodes to these outputs as CRTs can collect static charges very easily. The ARM7500 has LCD outputs for straight and splitscreen display types. These are connected to a 16 pin connector (P3) for conveience. Since there is no LCD standard connector, an adaptor must be made for each LCD pannel connected to the interface. This connector also has the signals for a genlock add-on circuit. The vertical sync will reset when the SINK pin is held high, but there is no similar circuit for the horizontal sinc. Horizontal sinc must be achieved by line locking with a dot clock PLL and phase detector on the horizontal sync pulses. This would be a great follow on project.

Page 5 audio Control and audio Power outputs.

Digitally controlled sound is found in most TVs . However, National Semi-Conductor will sell the LMC1982 to anyone with some bucks. With this part the sound output and balance can be controlled by a program and the computer user with "hot keys". The part is programmed by sending a serial stream from the ID bit on page one. Tone controlls could compenste for slower than normal sampling on the CD D/a circuits or compensate for small speakers. The audio section is rounded out with the LM2878, 5 watt per channel, audio amp. No puny sound out of this baby! Now the only problem is to figure out where to put the speakers.

Page 6 Expansion Slot and Logic analyser connectors

Since this board is to be used by people inventing unique applications (or porting old ones) for the ARM, I have provided an ISa like plug. all signals to the slot are buffered so as to not kill the 7500. This means that most existing board can be made to work. It is not completely ISa compatible as that would have required that the ARM7500 be redesigned, which is not the point of this board. Principal differences are: The board will only handle slave devices, no masters need apply. Only 2 "pseudo DMA" channels are handled by FIQ interrupts. No byte packing is done - that is the designer must know where the bytes are going in any port. Byte packing and unpacking are done in software. The addressing of the slot is carved out of the expansion memory in several segments for activating MEMR/W, IOR/W and DMA signals.

There is a 96pin connector that has a selection of the bus signals for expansion into a logic analyser pod. This could also be connected to a ROM emular or Writeable control store. ROM, DRAM and many IO operations can be decoded.

Page 7 Serial and Parallel ports.

The typical IO devices found in a PC are all compacted into "Super IO" or combo chips. I couldnat resist using one of these, and infact nether could Acorn. So I used the same one that they use (SMC37C665) - so sofware like RiscBSD would require less rewrite in these areas. On this page are the 2 serial ports. Port 1 is connected to a 9 pin Subminiature D connector ( J2) that is PC compatible and also found in all the other ARM development boards. The same serial hookup for VLSI and ARM PID and PIE boards can be used. The second seral channel is terminated by a 10 pin header (P14) tha can be connected to a 9pin or 25 pin D connector with mass terminated wire as found in many PC IO boards.

The Parallel port supported by the SMC37C665 is bi-directional and ECP compatible. With the proper software driver these emerging IEE-1285 interfaces would be supported. THe paralle port is terminated with a 26 pin header which translated to a 25 pin D connector with a short cable.

Page 8 Floppy and IDE interfaces.

The SMC37C665 has a PC compatible enhanced floppy controller with digital data seperator. I directly drives all normal floppy types up to 2.88Mbyte capacity. The RC7500 chassis mounts a simple 1.44 Mbyte 3.5 inch floppy.

There are 2 IDE interfaces. IDE1 is mapped in the combo's address space and the chip selects are produced by the 37C665 combo chip. IDE2 is mapped in the simple expansion space which means that 2 different master drives can be operated simultaneously for faster operation than a master/slave configuration (although 2 masters and 2 slave could be supported). Usually this is one hard drive and one ATAPI IDE CDROM drive.

Page 9 Ethernet Controller

Ethernet is all the rage now and is fairly inexpensive. The SMC92C92 supports both twisted pair and coaxial versions. The 10Base-T version of Ethernet uses shielded twisted pair wiring into star hubs. The board cost is minimal and it allows for an inexpensive and good perfoming LaN. With the proper software operating system and TCP/IP protocols, the RC7500 could be made into a workstation which can co-exist in the same network with Unix boxes and PCs -- and onto the Internet! The ethernet local address is stored in an 93C46 EEPROM which also has room for the Host ID - if one is ever needed. The 10 BaSE-T is terminated in a RJ-45 8 pin TELCO connector (J5) of which only 4 pins are used.

Page 10 Power and Left Overs

Power to the board is provided by a standard PC power connector which supplies +5, +12, -5 and -12 volts needed by the motherboard and by the expansion slot. a 4 Pin Disk drive connector can alos be used which only supplies the +5 and +12 volts need on the mother board.

Two 74HC377s are used to control the LED bar and the Joystick input load programming.

RC7500 Memory Map

The 512 Mbyte physical memory map of the RC7500 is divided broadly into ROM, IO and RAM spaces.

Instruction ROM space 0000,0000h to 01FF FFFFh and consists of 2, 16 MByte sections. 16 and 32 bit wide ROMs are supported. Flash is supported when the CS7500FE is used. The RC7500 does not have FLASH as the ARM7500 did not support that feature.

The DRAM space starts at 1000,0000h and ends at 1FFF FFFFh for a maximum space of 256 MBytes in 4 64 MBytes banks. Smaller DRAM bank are supported and can be made contiguous by using the ARM704 MMU. The RC7500 only has SIMM sockets for one DRAM bank made from one 72 pin SIMM socket

The Internal I/O space is divided into several sections. The ARM7500 supports the old address space of the original Acorn Computer IOC so that older software and peripherals will work with minimum rewriting. Old IO space runs from 0300,000 to 03FF FFFF and supports a mixture of internal and external peripherals. Extended external IO space runs from 0800 0000 to 0FFF FFFF. Main Memory Map

Physical address Range (Hex) Select signal Intended function
0000 0000 - 00FF FFFF Nromcs ROM 0 Main ROM
0100 0000 - 01FF FFFF Nromcs ROM 1 Extension ROM
0200 0000 - 02FF FFFF NvRAS VRAM not used in Next7500
0300 0000 - 0400 FFFF Nms/SIO/etc Internal and Local I/O
0800 0000 - 0FFF FFFF NeasisExtended IO Expansion used by Slot cards
1000 0000 - 1FFF FFFF NDRAS[3:0] DRAM banks 0-3, 64 MBytes each
2000 0000 - FFFF FFFF Memory map repeats

Slot Space

0800 0000 to 0BFF FFFFSlot MEMR/W Space, 64 Mbytes, with bits D31:16 missing
0C00 0000 to 0DFF FFFF Slot IOR/W Space, 32 Mbytes, with bits D31:16 missing
0E00 0000 to 0E00 002ESlot DMACK Space, 4 low active DMACKS and
high active TC decoded as chip selects.

DMAK Pins

0E00 0000 DACK00E00 0020 DACK0 + TC
0E00 0004 DACK10E00 0024 DACK1 + TC
0E00 0008 DACK20E00 0028 DACK2 + TC
0E00 000C DACK30E00 002C DACK3 + TC

Software Vectors

These addresses are fixed by the ARM processor and are usually mapped to RAM with the MMU

ADDRESS VECTOR INSTRUCTION DESCRIPTION

000 0000 Reset vector LDR PC,[PC, #Vector offset] Load Soft Vector to ROM Reset
000 0004 Undef Inst LDR PC,[PC, #Vector offset] Load Soft Vector to ROM FP Emulator
000 0008 Software Int LDR PC,[PC, #Vector offset] Load Soft Vector to SWI Dispatcher
000 000C abort Inst LDR PC,[PC, #Vector offset] Load Soft Vector to ROM routine
000 0010 abort Data LDR PC,[PC, #Vector offset] Load Soft Vector to ROM routine
000 0014 reserved
000 0018 Normal Int LDR PC,[PC, #Vector offset] Load Soft Vector to IRQ dispatcher
000 001C Fast Int LDR PC,[PC, #Vector offset] Load Soft Vector to FIRQ dispatcher

I/O Memory Map 0300 0000 to 03FF FFFF

General I/O area divided as below:

0300 0000 to 03FF FFFF Input Output Peripheral Functions
0301 0000 to 0301 FFFF COMBO Peripheral chip select
0301 2000 to 0302 9FFF COMBO Floppy DACK
0302 a000 to 0302 AFFF COMBO Floppy DACK + TC
0302 B000 to 0302 BFFF SCSI or Network Chip Select
0320 0000 to 0320 01F8Internal IOMDL registers (Interrupt, IO, control, and DMA)
0324 0000 to 0324 FFFF Extended Interrupt Sense and control.
0340 0000 to 0340 FFFF Internal VIDC2L registers ( Display Control)

ARM7500 IOC Registers Summary 320 0000 to 320 00FC

Internal IOC Register Map
NameAddress SizeReadWrite
IOCR00 8IOCRIOCR
KBDAT04 8KBDATINKBDATOUT
KBDCR08 8KBDCRKBDCR
IOPINS0CIOPINSIOPINEN
IRQSTA10 8IRQ StatusA ---
IRQRQA 14 8 IRQ ReqAIRQ clear A
IRQMSKA 18 8 IRQ MaskA IRQ MaskA
IDLEMD 1C 1 -Enter IDLE MODE.
IRQSTB20 8IRQ StatusB ---
IRQRQB 24 8 IRQ ReqB---
IRQMSKB 28 8 IRQ MaSK B IRQ MaSK B
STOPMD 2C 1- Enter STOP MODE
FIQST30 8FIQ Status ---
FIQRQ34 8FIQ Req---
FIQMSK 38 8 FIQ MaSK FIQ MaSK
CLKCTL 3C 8 CLKCTLCLKCTL
T0LOW40 8T0countLT0LatchL
T0HIGH44 8T0countHT0LatchH
T0GO48 0---T0Go Command
T0LAT4C 0---T0Latch
T1LOW50 8T1countLT1LatchL
T1HIGH54 8T1 CountH T1LatchH
T1GO58 0---T1Go
T1LAT5C 0---T1Latch
IRQSTC60 8IRQ StatusC ---
IRQRQC64 8IRQ ReqC---
IRQMSKC68 8IRQ MaskC IRQ MaskC
VIDCAUX6C 8VIDAUXVIDaUX
IRQSTD70 8IRQ StatusD ---
IRQRQD74 8IRQ ReqD---
IRQMSKD78 8IRQ MaskD IRQ MaskD
ROMCR080 8ROM Control 0 ROM Control 0
ROMCR184 8ROM Control 1 ROM Control 1
RESV88 8------
RFSHCR8C 8Refresh CR Refresh CR
ID0 94 8Chip ID Low byte ----
ID1 98 8Chip ID High byte ----
VERSION9C 8Chip Version----
MSDATA8 8MSDATINMSDATOUT
MSCRAC 8MSCRMSCR
reserved B0-BC
IOTCRC4 8IO TimingIO Timing
ECTCRC8 8Extended IO Timing Extended IO Timing
IOEXTCC 8IOEXTIO EXTENDED TIMING
DRAMWID D0 8DRAMWID DRRAMWID
SELFREFD4 8SELFREFSELFREF
JOYICRE0 8JOYICRJOYICR
JOYSRE4 8JOYSR---
JOYCCE8 8JOYCCJOYCC
JOYCNT0EC 16JOYCNT0---
JOYICR1F0 16JOYICR1---
JOYICR2F4 16JOYICR2---
JOYICR3F8 16JOYICR3---
reserved FC-17C

ARM7500 IOC DMA FUNCTIONS 320 0100 to 320 01F8
Name Address SizeRead Write
SDOCURA 180 32SDO 0 Current A SDO 0 Current A
SDOENDA 184 32SDO 0 End ASDO 0 End A
SDOCURB 188 32SDO 0 Current B SDO 0 Current B
SDOENDB 18C 32SDO 0 End BSDO 0 End B
SDOCR190 8SDO 0 ControlSDO 0 Control
SDOST194 8SDO 0 Status ---
CURSCUR 1C0 32Cursor CurrentCursor Current
CURSINIT 1C4 32Cursor InitCursor Init
VIDCURB 1C8 32VIDEO Current VIDEO Current
VIDCURA 1D0 32VIDEO Current VIDEO Current
VIDEND 1D4 32VIDEO End VIDEO End
VIDSTART 1D8 32VIDEO StartVIDEO Start
VIDINITA 1DC 32VIDEO INITVIDEO INIT
VIDCR1E0 8VIDEO ControlVIDEO Control
VIDINITB 1E8 32VIDEO INITVIDEO INIT
DMAST1F0 8DMA Status---
DMARQ1F4 8DMA IRQ ReqDMA IRQ Req
DMAMSK 1F8 8DMA IRQ MaskDMA IRQ Mask
0340 0000 VIDC internal functions

The VIDC has all write only rgisters accessed by writing to address 0340 0000.

0XXX XXXXVideo Palette VP
1000 00XXPAlette addressVPAR
2XXX XXXXReserved
3000 00XXLCD Offset Register 0 LOR0
3100 00XXLCD Offset Register 1 LOR1
4XXX XXXXBorder ColorBCR
5XXX XXXXCursor Palette Color 1 CPC1
6XXX XXXXCursor Palette Color 2 CPC2
7XXX XXXXCursor Palette Color 3 CPC3
8000 XXXXHorizontal Cycle Register HCR
8100 XXXXHorizontal Sync Width RegisterHSWR
8200 XXXXHorizontal Border Start RegisterHBSR
8300 XXXXHorizontal Display Start Register HDSR
8400 XXXXHorizontal Display End RegisterHDER
8500 XXXXHorizontal Border End RegisterHCER
8600 XXXXHorizontal Cursor Start Register HCSR
8700 XXXXReserved
8800 XXXXTest Register
8900 XXXXReserved
8C00 XXXXTest Register
9000 XXXXVertical Cycle Register VCR
9100 XXXXVertical Sync Width RegisterVSWR
9200 XXXXVertical Border Start RegisterVBSR
9300 XXXXVertical Display Start Register VDSR
9400 XXXXVertical Dosplay End RegisterVDER
9500 XXXXVertical Border End Register VBER
9600 XXXXVertical Cursor Start Register VCSR
9700 XXXXVertical Cursor End RegisterVCER
9800 XXXXTest Register
9A00 XXXXTest Register
9C00 XXXXTest Register
A000 000XSterio Image Register 0 SIR0
A100 000XSterio Image Register 1 SIR1
A200 000XSterio Image Register 2 SIR2
A300 000XSterio Image Register 3 SIR3
A400 000XSterio Image Register 4 SIR4
A500 000XSterio Image Register 5 SIR5
A600 000XSterio Image Register 6 SIR6
A700 000XSterio Image Register 7 SIR7
B000 000XSound Frequency RegisterSFR
B100 000XSound Control Register SCR
C00X XXXXExternal Register EXR
D000 XXXXFrequency Synthesis Register FSR
E00X XXXXControl Register VIDCR
F000 XXXXData Control Register DATCR
37C665 integrated functions0301 0000 to 0301 0FFC

The 37C665 is a commonly used PC peripheral combo chip that provides most of the built in I/O for PCs. This latest version of the part features vertical recording for floppies, allowing 2.88 Mbytes for DOS format and 3.2 Mbytes for RISC-PC format. These ports are at address locations 301 000 + PCPort x4, thus Serial port 1 at 3F8 to 3FF is translated to 0301 0FE0 to 0301 0FFC. all COMBO ports are 8 bits. IDE#1 data which is selected by the 37C665 is 16 bits wide.

37C665 Configuration Registers0301 0FE0 to 0301 0FFC

REG Name R/W Description
0FC0 CFGA W Chip Configuration register A - Config Register pointer
0FC4 CFGB W Chip Configuration register B - Config Register Data

37C665 Serial Port

1 0301 0FE0 to 0301 0FFC

20301 0BE0 to 0301 0BFC

The serial ports are

REG Name R/W Description
F/BE0RBR/THR R-W Receive Buffer Register - Transmitter Holding Register
F/BE4IERR/W Interupt Enable Register (Bidirectional)
F/BE8IIRR Interupt Identification (read only)
F/BECLCRR/W Line Control Register
F/BF0MCRR/W Modem Control Register
F/BF4LSRR/W Line Status Register
F/BF8MSRR/W Modem Status Register
F/BFCSRR/W Scratch Register
F/BE0DLABLR/W Baud Rate Divisor Latch LSB
F/BE4DLABHR/W Baud Rate Divisor Latch MSB

Floppy Disk Controller 0301 0FC0 to 0301 0FCC

The Floppy controller is a 765 compatible with data FIFO and vertical recording enhancements and internal digital data separator.

REG Name R/W Description
0FC0 FSTATAR Floppy Status Register a
0FC4 FSTATB R Floppy Status Register B
0FC8 FDORR/W Floppy Digital Output Register
0FCC FTDRR/W Floppy Compatible Tape Drive Register
0FD0 FMSRR Floppy Main Status Register
0FD0 FDSRW Floppy Rate Select Register
0FD4 FDATAR/W Floppy Data or command - could be FIFOed
0FD8 RESV
0FDC FDIRR Floppy Digital Input Register (bit 7 only)
0FDC FCCRW Floppy Configuration Control Register

IDE#1 IDE Hard Disk or IDE CD ROM 0301 07C0 to 0301 07CC

IDE Is derived from the original Western Digital controller in the 80286 powered PC-AT.

We use this design because IDE drives are cheaper and simpler than SCSI drives and the IDE interface consists of an address decoder and data buffers, rather than expensive custom IC,.

Task FIle Registers
REG Name R/W Description
07C0 IDDATA R/W Hard Disk Data is 16 bits wide.
07C4 IDERRR IDE Error register
07C4 IDPRECOMP W IDE Precompensation Cylinder (is probably ignored)
07C8 IDSECNT R/W IDE Sector Count Register
07CC IDSECTR/W IDE Starting Sector Number Register
07D0 IDCYLH R/W IDE Starting Cylinder Number High Byte
07D4 IDCYLLR/W IDE Starting Cylinder Number Low Byte
07D8 IDRVHD R/W IDE DRIVE/ HEaD Register
07DC IDSTATR IDE Status Register
07DC IDCOMW IDE Command Register

Miscelaneous AT registers are at the Floppy location
REG Name R/W Description
0FD8 FIXEDR Hard Disk Status
0FD8 FIXEDW Hard Disk extra control bits left out of stupid WD design
0FDC FDIRR Floppy Digital Input Register (bits 6:0)

37C665 Parallel Port 0301 09E0 to 0301 09E8

Extended Parallel port supports normal, PS/2, ECP and EPP modes.

REG Name R/W Description
09E0 PDOUTR/W Parallel Data Output/Input Register
09E4 PSTATR Parallel Status Register
09E8 PCONR/W Parallel Control Register
09EC PEPPAR/W Parallel EPP address Port
09F0 PEPPD0 R/W Parallel EPP mode data port 0
09F4 PEPPD1 R/W Parallel EPP mode data port 1
09F8 PEPPD2 R/W Parallel EPP mode data port 2
09FC PEPPD3 R/W Parallel EPP mode data port 3

IDE#2 Port0302 B000 to 0302 B01C

The 86 RC7500 provides for 2 IDE ports so that 2 IDE devices may be served at full speed without the overhead associated with slave IDE devices. It is intended that the IDE#2 Port be used with an IDE hard disk and the IDE#1 used with a CDROM drive with an IDE interface.

IDE#2 Task FIle Registers at IDE2CS0 (301B000 to 301B01C)

Data is 16 bits wide, Registers are 8 bits wide.

REG Name R/W Description
B800 IDDATA R/W Hard Disk Data is 16 bits wide.
B804 IDERRR IDE Error register
B804 IDPRECOMP W IDE Precompensation Cylinder (is probably ignored)
B808 IDSECNT R/W IDE Sector Count Register
B80C IDSECT R/W IDE Starting Sector Number Register
B810 IDCYLH R/W IDE Starting Cylinder Number High Byte
B814 IDCYLLR/W IDE Starting Cylinder Number Low Byte
B818 IDRVHD R/W IDE DRIVE/ HEaD Register
B81C IDSTAT R IDE Status Register
B81C IDCOMW IDE Command Register

Miscelaneous IDE#2 registers are at IDE2CS1 (301B020 to 301B03C)

REG Name R/W Description
B838 FIXEDR Hard Disk Status
B838 FIXEDW Hard Disk extra control bits left out of stupid WD design
B83C FDIRR Digital Input Register
Special Internal Functions

Internal Registers at IDE2CS2/3 (302B040 and 302B060) Registers are 8 bits wide.

REG Name R/W Description
B040 JOYCON W Control over functionality of joystick port from resistive analog input to a simple timer or external time delay.
B060 SETLEDS W Writing a 0 in this space will light up the coresponding 8 LEDs in a 10 LED Light Bar(for diagnostics).

Internal Registers at nSIOCS2 (324 0000 )

REG Name R/W Description
0000 FREQCONW Control over the Video Frequency generated by the clock chip, also Turbo and Power LEDs and audio control.
0000 EXTINTR Monitor Joystick buttons, turboswitch and Serial interrupts.
91C92 Ethernet Port 0302 B800 to 0302 B81C

The 86 RC7500 features Ethernet (10BaSE-T) for local area communication. This can be for debugging, software downloads, or for a full TCP/IP communication link. The 91C92 has 4 register banks of 16 registers for control and status and an internal 4608 byte RAM for transmit and receive FIFOas. The Ethernet base address is 301B800 and each register is 16 bits wide.

REG Bank0 NameR/W Description
00TCRR/W Transmit Control Register
04EPHR Status of last transmitted frame
08RCRR/W Receive Control Register
0CCOUNTER R Counter Register for Errors
10MIRR Memory Information Register
14MCRR/W Memory Congifuration Register
18RESERVED
1CBANK SELECT R/W Select 4 banks of registers

REG Bank1 NameR/W Description
00CONFIG R/W Hardware Configuration
04BASER/W I/O Base address and ROM size and address
08ADDRESS0 R/W Bytes 0 and 1 of local Ethernet address
0CADDRESS2 R/W Bytes 2 and 3 of local Ethernet address
10ADDRESS4 R/W Bytes 4 and 5 of local Ethernet address
14GENPURP R/W a 16 bit GP R/W register
18CONTROL R/W Ethernet function programming
1CBANK SELECT R/W Select 4 banks of registers

REG Bank2 NameR/W Description
00MMUCOM W Command and MMU Register
04PNR/ARR R/W Packet Number Register, allocated Packet Number Register
08FIFO_POINT R RX and TX packet numbers
0CPOINTER R/W Local SRAM address and direction control, Will auto increment
10DATAR/W SRAM read or write data.
14DATA Mapped twice for load or store multiple commands.
18INTERRUPT R-W Interrupt cause/reset register/ Interrupt Mask register
1CBANK SELECTR/W Select 4 banks of registers

REG Bank3 NameR/W Description
00 Multicast R/W 8 Multicast address Table
04 TABLE
08-
0C-
10 NU
14 NU
18 NU
1C BANK SELECTR/W Select 4 banks of registers

Input/ Output Register Description

IOC Internal Operation and Control Registers

These registers are used to operate the external built in interfaces, the memory control, the timer, interrupts, and DMA registers for the Next7500.

IOCR - IOC Control Register (address 320 0000)

This register senses the Raw FlyBack and Joystick Buttons and controls and senses the ID, I2CC and I2CD open drain pins.

REG

ADDR TYPE D7 D6 D5 D4 D3 D2 D1 D0
IOCR 0x00 R/W FLYBK NINDEX 1 1 ID 1 I2CC I2CD

The detailed description of the bits in this register follow:

Bit Name R/W Reset Use
7 FLYBK R x FLYBK Input is the status of the FLYBK pin before the edge trigger latch. This interupt is connected to the internal video flyback vertical retrace signal
6 BUTTONS R x Connected to the 4 Joystick Buttons. any button going low will set this interrupt input low.
5:4 RESV R 11 Bits 5 and 4 are internally connected to VDD
3 ID R 1 ID pin is open drain. Writing a 0 will maintain a 0 but writing a one may still mean that the pin could be 0 from an attached device. Connected to LMC1982 audio Controller Data pin.
2 RESV R 1 Internally connected to VDD
1 I2CC R/W 1 I2C Clock pin (Open drain) Connected to PCF8583 Clock plus SRAM chip. (see section 9.0)
0 I2CD R/W 1 I2C Data Pin (Open drain) Connected to PCF8583 Clock plus SRAM chip.

4.1.2 Keyboard Interface

KBDAT - Keyboard Data (address 320 0004)

MSDATA - Mouse Data (address 0320 00a8 )

Reading these registers sense the data from the keyboard/ Mouse and writing this register set the next byte to be sent to the keyboard or Mouse.

KBDCR - Keyboard Control Register (address 320 0008) and

MSCR - Mouse Control Register (address 320 00AC)

The keyboard interface uses two pins - KDATA and KCLK. The mouse interface uses two pins - MSDATA and MSCLK. all are open drain and can be driven by either the ARM7500 or the Keyboard. Direct access to the keyboard pins is provided by the KDATA and NCLK bits. Direct access to the mouse pins is provided by the MSDATA and MSCLK bits. Writing a 0 takes the coresponding open drain pin low. Direct control of the keyboard or mouse pins is used to control and signal the keyboard or mouse. During transmission outgoing parity is automatically generated.

REG ADDR TYPED7D6D5D4D3D2D1D0
KBDCR008 R/W TXE TXB RXF RXB KENABL RXPAR KDATAKCLK
MSCR0AC R/W TXE TXB RXF RXB MSENABL RXPAR MSDATAMSCLK

The detailed description of the bits in this register follow:

Bit Name R/W Reset Use

7 TXE R x Transmit Register is empty and may be written. This bit may also cause an interrupt if enabled.

6 TXB R x Transmission is in progress.
5 RXF R x Receiver register is full - keyboard byte received. This bit may cause an interrupt if enabled.
4 RXB R x Receive in progress.
3 KENABL R/W 0 Enables the keyboard interface. This bit must be set for the keyboard interface to work. When low the keyboard state machine is held in reset state.
2 RXPAR R x Received parity. Used for checking data received from keyboard.
1 KDATA/ R/W 1 Writing 0 will force the KDATA or MSDATA pin low. MSDATA
0 KCLK/ R/W 1 Writing 0 will force the KCLK or MSCLK pin low.
MSCLK
IOPINS - IO PIN Status and Control (address 300 000C)

This register reads data that is on the IOP[7:0] pins. The IOP[7:0] are open drain so wrtiing a 1 to the register disables the pin driver and writing a 0 to the pin pulls it down.

REG ADDR TYPE D7 D6 D5 D4 D3 D2 D1 D0

IOPINS 000C R/W IOP[7] IOP[6] IOP[5] IOP[4] IOP[3] IOP[2] IOP[1] IOP[0]

The detailed description of the bits in this register follow:

Bit Name R/W Reset Use 7:0 IOP[7:0] R/W pullup Writing 0 drives the coresponding pin low.

Writing 1 disables the pin driver.

Reading reads the current pin data. Interrupt Registers

Each group of registers used to detect and control ARM interrupt comes in a group. The status register of each group reflects the state of the internal and external interrupt sources. The Mask register enables individual interrupts bits. The Request register shows the and of corresponding Status bits and Mask bits, so it is used by the interrupt handler to detect actual active interrupts. The reset register is used to reset internal or edge sensitive interrupts individually (to prevent interrupt races). Both internal interrupts and external level sensitive interrupts must be cleared before exiting the interrupt routine or a re-interrupt will occur and the controller will probably hang up, causing the programmer to scratch his head and the user to become irate

IRQ Group A - addresses 320 0010 to 320 0018

IRQSTA - IRQ Raw Status a (address 300 0010) - Reading this register reflects the actual status of the interrupts connected to this register.

IRQRQA - IRQ Request a (address 300 0014) - Reading this register reflects the masked status of the interrupts connected to this register. Set bits are ORed to contribute to the IRQ output to the ARM proceaar.

IRQCLA - Clear IRQ a bits (address 300 0014) - This write only register clears the internal interrupts connected to group a and reflected in the IRQSTa and IRQRQA registers.

IRQMSKA - IRQ Mask Register a (address 300 0018) - This read/write register reflects the mask used to control the interrupts connected to group a.

IRQ Group a Registers

REG ADDR TYPE D7 D6 D5 D4 D3 D2 D1 D0

IRQSTA 0x10 R/O 1 TM[1] TM[0] POR FLYBK nINT1 0 INT2

IRQRQA 0x14 R/C 0 TMR[1] TMR[0] PORR FLYBKR nINT1R 0 INT2R

IRQCLA 0x14 W/O - TMC[1] TMC[0] PORC FLYBKC nINT1C - INT2C

IRQMSKA 0x18 R/W - TMM[1] TMM[0] PORM FLYBKM nINT1M - INT2M

IRQ Group a Bit Description

The detailed description of the bits in this IRQ group follow:

Bit Name R/W Reset Use

7 Set Bit -- 1 can be used for FIQ to IRQ downgrade

6 TM[1] R/C 0 Timer 1 Reload sets this bit. Write bit 6 at IOC address 0x14 to reset this bit.

5 TM[1] R/C 0 Timer 0 Reload sets this bit. Write bit 5 at IOC address 0x14 to reset this bit.

4 POR R/C 1 Power On Reset. Write 1 to bit 4 at IOC address 0x14 to reset this bit. NRESET does not set this bit.

3 FLYBK R/C 0 Flyback rising edge from VIDC20 has been received. Write to bit 3 at IOC address 0x14 to reset this bit.

2 nINT1 R/C 0 nINT1 falling edge pulse received - used to detect Joystick button press. after reading Interrpt Extention register, write to bit 2 at IOC address 0x14 to reset this bit.

1 RESV -- 0 Not Used

0 INT2 R/C 0 INT2 used for Printer Interrupt rising edge detected. Write to bit 0 at IOC address 0x14 to reset this bit.

IRQ Group B - addresses 320 0020 to 320 0038

IRQSTB - IRQ Raw Status B (address 320 0020) - Reading this register reflects the actual status of the interrupts connected to this register.

IRQRQB - IRQ Request B (address 320 0024) - Reading this register reflects the masked status of the interrupts connected to the IRQSTB register and anded with the IRQMSKB register . Set bits are ORed to contribute to the IRQ output to the ARM processor.

IRQMSKB - IRQ Mask Register B (address 300 0028) - This read/write register reflects the mask used to control the interrupts connected to group B

REG ADDR TYPE D7 D6 D5 D4 D3 D2 D1 D0

IRQSTB 0x20 R/O KBRX KBTX nINT3 nINT4 INT5 nINT6 INT7 nINT8

IRQRQB 0x24 R/O KBRX KBTX nINT3 nINT4 INT5 nINT6 INT7 nINT8

IRQMSKB 0x28 R/W KBRX KBTXM nINT3M nINT4M INT5M nINT6M INT7M nINT8M

IRQ Group B Bit Description

The detailed description of the bits in this IRQ group follow:

Bit Name R/W Reset Use

7 KBRX R/M x Keyboard Has received Data. Read keyboard to clear.

6 KBTX R/M x Keyboard Transmitter Empty. Write keyboard to clear (or reset KBTXM bit)

5 nINT3 R/M x nINT3 pin is Low. This interrupt is used for both serial channels. If either serial channel has an interrupt this pin will go low. Read the Interrupt Extension register to determine which channel has caused the interrpt and service the serial channel to reset the interrupt.

4 nINT4 R/M x nINT4 pin is low. This interrupt is connected to the floppy section of the combo chip. Service the floppy to reset this interrupt.

3 INT5 R/M x INT5 Interrupt pin is high. This interrupt is connected to the SMC91C92 Ethernet Controller.

2 nINT6 R/M x nINT6 Interrupt pin is low. This is connected to the inverse of the DREQ3 pin in the Expansion Slot connector.

1 INT7 R/M x INT7 Interrupt pin is high. This pin is connected to the IDE channel 1 interrupt.

0 nINT8 R/M x nINT8 pin is low. This pin is connected through an inverter to the DREQ3 pin in the Expansion Slot connector.

FIQ Group - addresses 320 0030 to 320 0038

FIQST - FIQ Raw Status B (address 300 0030)

Reading this register reflects the actual status of the interrupts connected to this register.

FIQRQ - FIQ Request (address 320 0034)

Reading this register reflects the masked status of the interrupts connected to this register. Set bits are ORed to contribute to the IRQ output to the ARM processor.

FIQMSK - FIQ Mask Register (address 320 0038)

This read/write register reflects the mask used to control the interrupts connected to group B.

REG ADDR TYPE D7 D6 D5 D4 D3 D2 D1 D0

FIQST 0x30 R/O 1 nINT8 0 nINT6 0 0 INT5 INT9

FIQRQ 0x34 R/O 1 nINT8 0 nINT6 0 0 INT5 INT9

FIQMSK 0x38 R/W FFIQM nINT8FM 0 nINT6FM 0 0 INT5M INT9M

FIQ Group Bit Description

The detailed description of the bits in the FIQ group follow:

Bit Name R/W Reset Use

7 FFIQ -- 1 Forced FIQ used for testing the FIQ channel (always set)

6 nINT8 R/M x nINT8 pin is Low. This interrupt is connected to the DREQ3 pin

5 RESV R 0 Not Used

4 nINT6 R/M x nINT6 pin is Low. This interrupt is connected to the DREQ2 pin.

3 RESV R 0 Not Used

2 RESV R 0 Not Used

1 INT5 R/M x INT5 Interrupt is high. This interrupt is connected to the SMC91C92

0 INT9 R/M x INT9 is connected to the Floppy Disk Data Request. (pseudo DMA)

IRQ Group C - addresses 320 0060 to 320 0068

IRQSTC - IRQ Raw Status C (address 320 0060)

Reading this register reflects the inverse of the IOP pin state (if IOP[0] is low then bit[0] is high).

IRQRQC - IRQ Request C (address 320 0064)

Reading this register reflects the masked status of the interrupts connected to the IRQSTC register and anded with the IRQMSKC register . Set bits are ORed to contribute to the IRQ input to the ARM7 processor.

IRQMSKC - IRQ Mask Register C (address 300 0068)

This read/write register reflects the mask used to control the interrupts connected to group C

REG ADDR TYPE D7 D6 D5 D4 D3 D2 D1 D0

IRQSTC 0x60 R/O NIOP[7] NIOP[6] NIOP[5] NIOP[4] NIOP[3] NIOP[2] NIOP[1] NIOP[0]

IRQRQC 0x64 R/O NIOP[7] NIOP[6] NIOP[5] NIOP[4] NIOP[3] NIOP[2] NIOP[1] NIOP[0]

IRQMSKC 0x68 R/W IOP[7]M IOP[6] IOP[5]M IOP[4]M IOP[3]M IOP[2]M IOP[1]M IOP[0]M

FIQ Group Bit Description

The detailed description of the bits in the FIQ group follow:

Bit Name R/W Reset Use

7 NIOP[7] R/M x IDE2IRQ

6 NIOP[6] R/M x Connected to Expansion Slot IRQ10

5 NIOP[5] R/M x Connected to Expansion Slot IRQ9

4 NIOP[4] R/M x Connected to Expansion Slot IRQ7

3 NIOP[3] R/M x Connected to Expansion Slot IRQ6

2 NIOP[2] R/M x Connected to Expansion Slot IRQ5

1 NIOP[1] R/M x Connected to Expansion Slot IRQ4

0 NIOP[0] R/M x Connected to Expansion Slot IRQ3

IRQ Group D - addresses 320 0070 to 320 0078

IRQSTD - IRQ Raw Status D (address 320 0070)

Reading this register reflects actual status of the interrupts connected to this register.

IRQRQD - IRQ Request D (address 320 0074)

Reading this register reflects the masked status of the interrupts connected to the IRQSTD register and anded with the IRQMSKD register . Set bits are ORed to contribute to the IRQ input to the ARM7 processor.

IRQMSKD - IRQ Mask Register D (address 300 0078)

This read/write register reflects the mask used to control the interrupts connected to group C

REG ADDR TYPE D7 D6 D5 D4 D3 D2 D1 D0

IRQSTD 0x70 R/O 0 0 0 NEVENT2 NEVENT1 AtoD MSTXE MSRXF

IRQRQD 0x74 R/O 0 0 0 NEVENT2 NEVENT1 AtoD MSTXE MSRXF

IRQMSKD 0x78 R/W 0 0 0 NEVENT2M NEVENT1M AtoDM MSTXEM MSRXFM

IRQ Group D Bit Description

The detailed description of the bits in this IRQ group follow:

Bit Name R/W Reset Use

7:5 RESV -- 0 Not Used

4 NEVENT2 R/M x NEVENT2 pin is low. This pin is connected to the PANIC button.

3 NEVENT1 R/M x NEVENT1 pin is low. This pin is connected to the RTC interrupt.

2 AtoD R/M x Joystick Comparator Interrupt

1 MSTXE R/M x Mouse transmitter empty

0 MSRXF R/M x Mouse receiver full TIMERS (addresses 320 0040 to 005C)

The ARM7500 Timers are dual 16 bit counters that are clocked from a 2 MHz clock (Clock 64 divided by 32). asociated with each counter are two 8 bit timer preset registers and two 8 bit timer capture registers. Writing the TnLOW sets the timer preset register for bits 7-0 and writing the TnHIGH sets the preset register for the bits 15-8. Reading the TnLOW register accesses the lower capture register and reading the TnHIGH register accesses the high capture register. Each timer counter decrements continuously. When it it hits zero it is reloaded from the Timer Latch registers. Each reload event is reflected in the IRQSTa register for TM[1:0]. These bits must be cleared before leaving the interrupt service routine by writing set bits to the IRQCLa register. By writing to the timer GO location. the repective time is reloaded imediately with the values in the latch register. The current value of the timer counter may be read by writing to the Latch command location. This transfers the present count to the 2 capture registers, which than may be read without disturbing the counter. The maximum timeout value is 2^16 or 30 milliseconds. (pretty short eh?)

Timer 0 (320 0040 to 320 004C)

REG ADDR TYPE D7 D6 D5 D4 D3 D2 D1 D0

T0LOW 0040 R/W T0[7] T0[6] T0[5] T0[4] T0[3] T0[2] T0[1] T0[0]

T0HIGH 0044 R/W T0[15] T0[14] T0[13] T0[12] T0[11] T0[10] T0[9] T0[8]

T0GO 0048 W -- -- -- -- -- -- -- --

T0LAT 004C W -- -- -- -- -- -- -- --

Timer 1 (320 0050 to 320 005C)

REG ADDR TYPE D7 D6 D5 D4 D3 D2 D1 D0

T1LOW 0040 R/W T1[7] T1[6] T1[5] T1[4] T1[3] T1[2] T1[1] T1[0]

T1HIGH 0044 R/W T1[15] T1[14] T1[13] T1[12] T1[11] T1[10] T1[9] T1[8]

T1GO 0048 W -- -- -- -- -- -- -- --

T1LAT 004C W -- -- -- -- -- -- -- -- ROM Control Registers (320 0080 to 320 0084):

These registers are used to program the Instruction ROM options. The ARM7500 supports control of two 16MByte banks of ROM, even though there is only 1 NROMCS pin. With the standard 32 MHz master clock, the ROM banks can be programmed from 220ns accesss time to 31.25 ns access time. To accelerate accesses, burst mode ROM accesses are supported. ROM acesses can be in 32 bit or 16 bit modes. When in 16 Bit modes the ROM is accessed twice for each read. Normally ROMs are address from LA[2] and up. In 16 bit mode the LA[2] pin is derived internally from LA[1] through an internal mux. The ROM resets to 16 bit mode so that in 32 ROM systems the first code must set the ROMCS to the proper operational mode.This switch is tricky and will be elucidated later.

Bank 0 covers the address space 0000 0000 to 00FF FFFF and bank 1 covers the addesses 0100 0000 to 01FF FFFF.

REG ADDR TYPE D7 D6 D5 D4 D3 D2 D1 D0

ROMCR0 0x80 R/W 0 ROMW ROMSPD BRST1 BRST0 RSP2 RSP1 RSP0

ROMCR1 0x84 R/W 0 ROMW ROMSPD BRST1 BRST0 RSP2 RSP1 RSP0

a detailed description of the bits in these registers follows:

Bit Name R/W Reset Use

7 RESV R 0 Reserved

6 ROMW R/W 1 ROM Width, 0=32 bits, 1= 16 bits

5 ROMSPD R/W 0 ROM Speed, 0=half speed, 1=full speed

4:3 BURST R/W 00 Burst Control

0 0Burst Off

0 1125 ns

1 093.75 ns

1 162.5 ns

2:0 RSP R/W 000 ROM access timing

0 0 0 218.75 ns

0 0 1 187.5 ns

0 1 0 156.25 ns

0 1 1 125 ns

1 0 0 93.75 ns

1 0 1 62.5 ns DRAM Control

The MA[11:0] pins reflect the ARM address in the following manner.

Four 1-64MB DRAM Banks

MEMAD MA11 MA10 MA9 MA8 MA7 MA6 MA5 MA4 MA3 MA2 MA1 MA0

ROW 24 22 19 18 17 16 15 14 13 12 11 10

COL 25 23 21 20 9 8 7 6 5 4 3 2

DRAM memory decode:

RAS Enable A[29:26]CAS Enable NBW A[1:0]

NRAS00100 NCAS00 00

NRAS00100 NCAS00 00

NRAS10101 NCAS10 01

NRAS20110 NCAS20 10

NRAS30111 NCAS30 11

NCAS[3:0] 1 xx

RAMREF RAM Refresh Control Register (320 008C):

This register is used to program the refresh rate of the DRAM sub-system.

REG ADDR TYPE D7 D6 D5 D4 D3 D2 D1 D0

RAMREF 0x8C R/W 0 0 0 0 RATE3 RATE2 RATE1 RATE0

The detailed description of the bits in this register follow:

Bit Name R/W Reset Use

7:4 RESV R 0

3:0 REFRESH R/W 0000 RATE Refresh rate

0 0 0 0 Refresh Off

0 0 0 1 16 usec

0 0 1 0 32 usec

0 1 0 0 64 usec

1 0 0 0 128 usec

other values not defined?????????

Note: IOCLK=32 MHz Clock Prescaller = div1

DRAMCR RAM Operation Control Register (320 00D0):

This register is used to program the operation of the DRAM sub-system.

REG ADDR TYPE D7 D6 D5 D4 D3 D2 D1 D0

DRAMCR 0xD0 R/W 0 PRE RCD EDO DWID3 DWID2 DWID1 DWID0

The detailed description of the bits in this register follow:

Bit Name R/W Reset Use

7 RESV R 0

6 PRE R/W 0Precharge control 0=3 MEMCLK, 1=4 MEMCLK

5 RCD R/W 0Ras to Cas Delay 0=2 MEMCLK, 1=3MEMCLK

6 EDO R/W 0EDO mode0=Fast Page, 1=EDO operation

3:0 DIWD[3:0] R/W 0000 DRAM Width. 0=32 bits, 1=16 bits

SELFREF Self Refresh Control Register (320 0094):

This register is covered in section 3.16.4

3.6 Revision ID Registers (ID0, ID1, REV)3.6 Revision ID Registers (ID0, ID1, REV) (320 0094 to 320 009C):

The bits of the Revision ID Register are defined as follows:

REG ADDR TYPE D7 D6 D5 D4 D3 D2 D1 D0

ID00x94 R ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0

ID10x98 R ID15 ID14 ID13 ID12 ID11 ID10 ID9 ID8

REV 0x9C R REV7 REV6 REV5 REV4 REV3 REV2 REV1 REV0 Joystick Port Registers (analog input)

The ARM7500 contains a simple single slope integration a to D system for use with standard PC compatible Joysticks. 4 chanels are provided for the support of two joysticks or a more complicated interface. Each pin has an open drain clamp , a comparator and a 16 bit counter clocked with the CLK2 signal. When activated the open drain transistor releases the pin which then charges a capacitor through the joystick channel resistor. When the comparator threshhold is reached the counter stops and a channel interrupt is generated. The interrupts are combined in different ways for various type of operation. This method is inherently better than the PC because it doesnat disable interrupts and count the joystick poulse width in software. The maximum count is 2^16 or 65,536. This make a maximum conversion time of 32.768 msec with the 2 MHz count clock. Thus, up to 30 conversions per second can be made.

Joystick Interrupt Control Register (JOYICR ); (320 00E0):

This register is used to program the DMA Override and the External Peripheral Port select functions.

REG ADDR TYPE D7 D6 D5 D4 D3 D2 D1 D0

JOYCR 00E0 R/W JIC7 JIC6 JIC5 JIC4 JEN3 JEN2 JEN1 JEN0

a detailed description of the bits in this register follows:

Bit Name R/W Reset Use

7 JIC7 R/W 0 Joystick Interrupt when Ch3 and Ch2 are done

6 JIC6 R/W 0 Joystick Interrupt when Ch1 and Ch0 are done

5 JIC5 R/W 0 J-I when Ch3 and Ch2 and Ch1 and Ch0 are done

4 JIC4 R/W 0 J-I when Ch3 OR Ch2 OR Ch1 OR Ch0 are done

3:0 JEN[3:0] R/W 0000 Joystick Enable for channels 3 through 0. When all 4 channels are disabled then the comparator power is shut down.

Joystick Status Register (JOYSR ); (320 00E4):

This register is used to detect the status of the joystick converted channels.

REG ADDR TYPE D7 D6 D5 D4 D3 D2 D1 D0

JOYSR 00E4 R/W JRQ3 JRQ2 JRQ1 JRQ0 JRQS3 JRQS2 JRQS1 JRQS0

a detailed description of the bits in this register follows:

Bit Name R/W Reset Use

7:4 JRQ[3:0] R 0000 Joystick Request for channels 3 though 0, Indicates that the corresponding channel has generated an interrupt.

3:0 JRQS[3:0] R 0000 Joystick Request and Stop Flag for channels 3 though 0, Indicates that the corresponding channel has generated an interrupt. Stop Flag is generated by the programmed JOYICR conditions.

Joystick Counter Control (JOYCC ); (320 00E8):

This register is used to program the DMA Override and the External Peripheral Port select functions.

REG ADDR TYPE D7 D6 D5 D4 D3 D2 D1 D0

JOYSR 00E4 R/W JD3 JD2 JD1 JD0 JCR3 JCR2 JCR1 JRCR0

a detailed description of the bits in this register follows:

Bit Name R/W Reset Use

7:4 JD[3:0] R/W 0000 Joystick Discharge Control for channels 3 though 0, 0=open drain transistor off, 1=transistor on (discharge on)

3:0 JCR[3:0] R/W 0000 Joystick Counter Reset for channels 3 though 0, Writing a "0" Resets the corresponding joystick channel counter to 0. Writing a "1" enables the corresponding counter to count.

Joystick Counters (JOYCNTn ) (320 00EC to 320 00F8) JOYCNT0 00EC JOYICR1 00F0 JOYICR2 00F4 JOYICR3 00F8

These registers are read as 16 bit values. Since they are ripple Counters, they should not be read untill the corresponding channel has stopped. IO Control Registers

DMA Timing Register (DMATCR ) (320 00C0)

This register is used to program the DMA Override and the External Peripheral Port select functions.

REG ADDR TYPE D7 D6 D5 D4 D3 D2 D1 D0

DMATCR 0008 R/W DAT31 DAT30 DAT21 DAT20 DAT11 DAT10 DAT01 DAT00

a detailed description of the bits in this register follows:

Bit Name R/W Reset Use

7:6 DAT3[1:0] R/W 00 DMA Channel 3 Timing

0 0 Type a 4 * CLK16 = 240ns IOR/W

0 1 Type B 3 * CLK16 = 187ns IOR/W

1 0 Type C 2 * CLK16 = 133ns IOR/W

1 1 Type D 1 * CLK16 = 66ns IOR/W

5:4 DAT2[1:0] R/W 00 DMA Channel 2 Timing. See above table.

3:2 DAT1[1:0] R/W 00 DMA Channel 1 Timing. See above table.

1:0 DAT0[1:0] R/W 00 DMA Channel 0 Timing. See above table.

Local I/O Timing Register (IOTCR) (320 00C4)

This register programs the wait states for the Local system peripherals.

REG ADDR TYPE D7 D6 D5 D4 D3 D2 D1 D0

IOTCR 00C4 R/W 0 0 SNT1 SNT0 CMBT1 CMBT0 NET1 NET0

a detailed description of the bits in this register follows:

Bit Name R/W Reset Use

7:6 RESV R 00 Not Used

5:4 SNT[1:0] R/W 00 NSNDCS (Sound Port) Timing. See above DMA table.

3:2 CMBT[1:0] R/W 00 NCCS (Combo) Timing. See above DMA table.

1:0 NET[1:0] R/W 00 NNETCS (NET) Timing. See above DMA table.

Extended I/O Timing Register (ECTCR) (320 00C8):

This register programs the raw wait states for the extended address space external peripherals. Each bit controls the timing of a 16 Mbyte segment selected by LA[26:24]

REG ADDR TYPE D7 D6 D5 D4 D3 D2 D1 D0

IOTCR 0008 R/W IOT7 IOT6 IOT5 IOT4 IOT3 IOT2 IOT1 IOT0

a detailed description of the bits in this register follows:

Bit Name R/W Reset Use

7 IOT7 R/W 0 Extended IO Channel 7 Timing

(0F00 0000 to 0FFF FFFF - selected by LA[25:24])

0 Type a 4 * CLK16 = 240ns IOR/W

1 Type C 2 * CLK16 = 133ns IOR/W

6 IOT6 R/W 0 Ext IO Channel 6 Timing (0E00 0000 to 0EFF FFFF)

5 IOT5 R/W 0 Ext IO Channel 5 Timing (0D00 0000 to 0DFF FFFF)

4 IOT4 R/W 0 Ext IO Channel 4 Timing (0C00 0000 to 0CFF FFFF)

3 IOT3 R/W 0 Ext IO Channel 3 Timing (0B00 0000 to 0BFF FFFF)

2 IOT2 R/W 0 Ext IO Channel 2 Timing (0a00 0000 to 0aFF FFFF)

1 IOT1 R/W 0 Ext IO Channel 1 Timing (0900 0000 to 09FF FFFF)

0 IOT0 R/W 0 Ext IO Channel 0 Timing (0800 0000 to 08FF FFFF)

I/O Cycle End Timing Register (IOEXTND) (320 00CC):

This register adds a post prescaller clock period (nominally 32 Mhz) to the end of IO cycles to increase address hold time. Bit 7 is the only active bit..

REG ADDR TYPE D7 D6 D5 D4 D3 D2 D1 D0

IOEXTND 00CC R/W EXTND 0 0 0 0 0 0 0

Video auxillary Control Register (VIDCaUX) (320 006C):

This register controls the video and sound external clocks presented to the VID20L.

REG ADDR TYPE D7 D6 D5 D4 D3 D2 D1 D0

IOEXTND 00CC R/W 0 0 0 0 0 0 NEUR EDMUX

a detailed description of the bits in this register follows:

Bit Name R/W Reset Use

7-2 RESV R 0 Reserved - Not Used

1 NEUR R/W 0 Sets the external format for using a CD ROM 16 bit serial sound DaC. 0=European format, 1=Japan (The TDa1543 is European format.)

0 EDMUX R/W 0 EDMUX ESEL0ESEL1

0EREG0 EREG1

1PIXCLKEREG1 DMA Controller (addresses 320 0180 to 320 001F8)

The DMA controller contains Sound channel and Video and Cursor channels. The Sound channel has two sets of pointers "a" and "B" of a 29 bit current address pointer and a 12 bit end pointer. The current address is split into two parts a 17 bit PAGE address and a 12 bit OFFSET address. The OFFSET address increments by 1,2,or 4 bytes and is compared with the 12 bit END register on each transfer. If more than a full page is to be transferred the end point should be placed on the last address in the page and the B DMA address registers are programmed to complete or continue the DMA transfer. When the a pointer set is finished it can be filled with another set of pointers. Each pair of registers is used alternately.

Sound DMA Registers

(SDOCURA, SDOENDA, SDOCURB, SDOENDB, SDOCR, SDOST)

The DMA registers in the sound channel are as follows:

Channel address Registers:

REG ADDR TYPE D28:12 D11:0

SDOCURA 0180 R/W PageA[28:12] OffsetA[11:4] zero[3:0]

SDOENDA 0184 R/W Don't Care EndA[11:4] zero[3:0]

SDOCURB 0188 R/W PageB[28:12] OffsetB[11:4] zero[3:0]

SDOENDB 018C R/W Don't Care EndA[11:4] zero[3:0] Sound Channel Status and control registers:

REG ADDR TYPE D7 D6 D5 D4 D3 D2 D1 D0

SDOCR 0190 R/W DCLEAR DMWRT DENABLE 1 0 0 0 0

SDOST 0194 R/W DCLEAR DMWRT DENABLE DINC[4] DINC[3] DINC[2] DINC[1] DINC[0]

The DMAnCR and DMAnST detailed bit definition is as follows:

SDOCR (320 0190)

Bit Name R/W Reset Use

7 ENSTATE R/W 0 Reads 0, write 0=disable, 1=enable state machine

6 DMWRT R 0 0=Read data to Sound Channel

5 DENABLE R/W 0 1=DMA Channel is enabled.

4:0 DINC[4:0] R 10000 Quad Word (4 words) per DMA transfer

SDOST (320 0194)

REG ADDR TYPE D7 D6 D5 D4 D3 D2 D1 D0

DMAnST 0194 R 0 0 0 0 0 DOVER DINT A/B

Bit Name R/W Reset Use

7:3 RESV R 0 Reserved

2 DOVER R 1 SND Overrun. The Current set of pointers finished but the next set were not programmed.

1 DINT R 1 SND DMA Interrupt. a set of pointers has finished. In order to clear this bit the next pointers are programmed. They can be dummy values if the DMA is not enabled or finished.

0 A/B R 0 0=A pointers are in use, 1= B pointers are in use

DMA State Machine:

The state machine is intialized to state 110. The driver software writes 1 buffer full of data then enables the Interrupt. When the interrupt routine is entered the state is used to determine which set of buffer pointers are to be updated. The Interrupt routine signals the driver after each DMA pointer update so that the next buffer will be filled.

In the diagram below the lowest bit is used to determine which pointers are updated. Initially SD0CURA and SD0ENDA are updated which resets the Overrun bit. The Interrupt routine is then reentered and updates the SD0CURB and SD0ENDB pointers. At this point the interrupt is reset until channelA finishes. The normat program flow path is to write A and B alternately untill the last buffer. The SD0END register is programmed with the Stop bit set. At the last interrupt the alternate pointers are written mearly to reset the interrupt. The state machine and the DMAMSK are then both disabled. Cursor DMA

There are two DMA registers used to control the cursor. CURCUR - current cursor DMA pointer and CURINIT - the initial cursor pointer value. Cursor data is used when the VNC pin is low when the VIDRQ is generated by the VIDC20. The CURCUR register is returned to the CURINIT pointer on each flyback signal. The actual cursor position is programmed in the VIDC20. Cursor data can be programmed to come from DRAM or VRAM.

Cursor DMA address Registers:

REG ADDR TYPE D28:4 Don't Care

CURCUR 01C0 R/W CURCUR[28:4] zero[3:0]

CURINIT 01C4 R/W CURINIT[28:4] zero[3:0]

Video DMA

There are 5 registers used to control the vidio DMA interface which work with the VIDC20L internal video controller to generate low, medium and high definition screens using DRAM. The designated Video RAM must fit within a 16 Mbyte segment of DRAM. The VIDSRT register is programmed with the start of the video screen, This must be a quad word boundary (16 Bytes).

VIDINIT is programmed with the actual start of the first pixel shown on the screen. It is programmed on 16 byte boundaries. During Flyback VIDCUR in intialized to the VIDINIT register. VIDCUR len increments by the init value in VIDCR untill the VIDEND is reached or the VIDC20 comes to the end of the frame. If VIDEND is reach the VIDCUR is loaded with the VIDSRT value and continues to increment. The data is wrapped around the region defined by VIDSRT and VIDEND. If the VIDINIT is set to above the VIDEND value becaus the start of the screen is in the last half SaM then the L bit in the VIDINT must be set. In VRAM mode bits [7:0] of VIDEND are not compared.

REG ADDR TYPE D31:24 D28:0

VIDCURB 01D0 R/W X X X PG[28:24] VIDCURB Offset[23:0]

VIDCURA 01D0 R/W X X X PG[28:24] VIDCURA Offset[23:0]

VIDEND 01D4 R/W X X X XXXXX VIDEND Offset[23:0]

VIDSRT 01D8 R/W 0 0 0 PG[28:24] VIDSRT Offset[23:0]

VIDINITA 01DC R/W 0 L 0 PG[28:24] VIDINITA Offset[23:0]

VIDINITB 01E8 R/W 0 L 0 PG[28:24] VIDINITB Offset[23:0] Video Control register:

REG ADDR TYPE D7 D6 D5 D4 D3 D2 D1 D0

VIDCR 01E0 R/W DPANEL RESV DENABLE DINC[4] DINC[3] DINC[2] DINC[1] DINC[0]

The VIDCR detailed bit definition is as follows:

VIDCR (320 01E0)

Bit Name R/W Reset Use

7 DPANEL R 0 0 = normal video, 1 = dual panel LCD support

6 RESV R/W 0 Not used

5 DENABLE R/W 0 Video and Cursor DMA Channels are enabled.

4:0 DINC[4:0] R/W 10000 DMA increment value is 1 quad word.

DMA Interrupt Registers

There is a set of interrupt registers that are dedicated to the DMA channels. For each channel there is a raw status bit, a request bit and a mask bit. There is 1 interrupting DMA channel. (New for the RC7500 ).

REG ADDR TYPE D7 D6 D5 D4 D3 D2 D1 D0

DMAST 01F0 R/O 0 0 0 SDO0 0 0 0 0

DMARQ 01F4 R/O 0 0 0 SDO0RQ 0 0 0 0

DMAMSK 01F8 R/W 0 0 0 SDO0M 0 0 0 0

DMA Software Channel Driver

There is a software driver that is needed to control the DMA channels. The listing is in appendix B. Clock Control Registers

There is a set of control registers that are dedicated to the operation of the ARM7500 clocks. Nominally all ARM7500 clocks are derived from the 32 MHz MEMCLK.

ARM7500 Reset and Power On Reset

There are tree external signals used for reset control on the RC7500 :

NPOR is used with and external RC network (plus diode to VCC). NPOR sets the NPOR flag in the IRQa interrupt registers and forces the CPUCLK, MEMCLK, and IOCLK prescallers into divide by two mode. all ARM7500 blocks are held in reset when NPOR is low. However DRAM refresh is maintained at the highest selectible rate. (16usec).

NRESET is both an input and opern drain output. When NPOR is low NRESET is driven low also. The state of NRESET is synchronized before being passed to the internal circuitry. NRESET hjold the the ARM CPU and VIDC2L in reset, but the IOMDL is only briefly reset and then generates DRAM refresh.

RESET output is the inverse of NRESET after the sycronizers.

During NPOR and NRESET, the ARM CPU is generate incrementing addresses without bus requests. Ether reset forces the IDLE MODE off and clock resume to all parts of the device.

ARM7500 Clock Generation

There are several clock used internally for operational flexibility. CPUCLK, MEMCLK and IOCLK have input prescallers acessable in CLKCTL register. It is expected that in most systems these three inputs will be connected to the same 32 Mhz external clock source. When the SNA pin is (1) the CPU is driven from the MEMCLK also. The frequency of CPUCLK is determined by the speed capability of the CPU and by by power conciderations. MEMCLK determines the performance of the connected DRAM and ROM. IOCLK is used as the master clock for fixed frequency functions such as the timer, mouse, keyboard, and IO clocks.

CPUCLK CPU core clock - is the same as the FCLK in ARM710. Has

MEMCLK Memory system clock - is used to drive the ROM and DRAM acess timing and provide MCLK for the CPU core.

IOCLK IO Interface clock - generates CLK2, CLK16, REF8, CLK8 - also generates the internal REFCLK to the VIDC2L.

VCLKI Video clock Input

HCLK alt video clock

SCLKI alt sound clock Input

ARM7500 Clock Modes

There are several power saving clock modes controlled by the IDLEMODE, STOPMODE , and CLKCTL registers. any power down mode is cancelled by the NPON and NRESET pins. These modes are sumarized below:

MODECPUCLK MEMCLK IOCLKOSCPOWER

NORMAL ONONONHIGH

IDLEOFFONONHIGH

STOPOFFOFFOFFLOW

Normal Mode

The ARM7500 is in NORMAL MODE after NPON or NRESET.

IDLE Mode

This is the first level of power saving. By stoping the CPU during idle time (between events), powere management can reduce the average chip power used. During IDLE MODE the DRAM refresh and display work normally. External IO can be programmed to stop by turning off CLK16, CLK8, REF8, and CLK2 that are derived from the IOCLK. The IDLE MODE is cancelled by NPON, NRESET, NEVENT[2:1] or internal NFIQ or NIRQ propagating to the CPU core.

STOP Mode

This is the lowest power mode. all Clocks are off. Video and Sound DACs are also off and do not consume static power. The external clock power pin is low, which can be used to gate the external chrystal oscillator off. Before entering STOPMODE the attached DRAM can be programmed to enter self refresh mode by manipulating the RAS and CAS lines directly with the SELFREF register. The STOP MODE is reset by NPOR, NRESET, or the NEVENT[2:1] pins. FIQ and IRQ do not affect this state. The CLKPOWER pin is used to control the ocillator power. The turn on of the clocks is regulated by the CLKDLY pin. During stop mode an open drain transistor keeps the voltage on an RC network low. When the NEVENT[2:1] happens the CLKPOWER pin goes high and the open drain on the CLKDLY releases. a voltage comparator connected to this pin keeps the internal power off while the RC network charges. When the threshold is reached the chip clocks are synchronouly enabled. Power Management Registers

The four registers below are used to control the power used by the ARM7500 system.

REG ADDR TYPE D7 D6 D5 D4 D3 D2 D1 D0

IDLEMD 001C R/W - - - - - - - IDCKCR

STPMD 002C R/W 0 0 SDO1M SDO0M IOD3M IOD2M IOD1M IOD0M

CLKCTL 003C R/W 0 0 0 0 0 CPUDIV MEMDIV IODIV

SELFREF 00D4 R/W NCAS3 NCAS2 NCAS1 NCAS0 NRAS3 NRAS2 NRAS1 NRAS0

IDLEMODE - CPU IDLE Mode Control (address 0320 001C)

Writing a 1 to this register will stop the FCLK - CPU Core clock. Writing a 0 to this register will stop CLK2, CLK8, REF8 and CLK16. IDLE MODE is terminated by a RESET, PON, EVENT1 or EVENT2, or a FIQ or IRQ interrupt input to the CPU reguarless of whether the CPU FIQ or IRQ is internally enabled in the CPSR.

STOPMODE - CPU Stop Mode Control (address 0320 002C)

Writing to this register will force the ARM7500 into STOP MODE - The data that is written will apear on the CPU D[31:0] pins and hold. The STOP MODE is reset by NPOR, NRESET, or the NEVENT[2:1] pins going low.

CLKCTL - CPU Clock Control (address 0320 003C)

Writing to this register sets prescaller modes for internal clocks

Bit Name R/W Reset Use

7:3 RESV R 0 Reserved

2 CPUDIV R/W 0 0=Divide CPUCLK by 2, 1= divide CPUCLK by 1

1 MEMDIV R/W 0 0=Divide MEMCLK by 2, 1= divide MEMCLK by 1

0 IODIV R/W 0 0=Divide IOCLK by 2, 1= divide IOCLK by 1

SELFREF - DRAM Self Refresh Control (address 0320 00D4)

Writing to this register sets NCAS[3:0] or NRAS[3:0] pins low.

Bit Name R/W Reset Use

7:4 NCAS[3:0] R/W 0 Writing a bit in this range will set the coresponding NCAS pin low. NPON and NRESET resets these bits to 0 or Off. Video and Sound Funtions

The ARM7500 has extensive video capabilties n

The video and sound macrocell registers

The video and sound macrocell contains 296 write-only registers. (oh boy!) These are split into 2 categories; the 256 28-bit video palette entries, and the remaining control registers. (not that bad!) The video palette entries are written via an auto-incrementing address pointer. all the other registers (including the 28-bit cursor palette) are written directly with the address encoded in the top 4 or 8 bits of the data word. To program the registers, the ARM7500 address bus should be set to between 0x03400000 and 0x034FFFFF, and the data word written should include the individual register address in the upper 4 or 8 bits, as appropriate.

In order to define the display format correctly, thirteen_ registers need to be programmed as shown in the diagram below:

Register NAMECGAVGASVGA BVGA

Frequency Control RegisterFREQCON X0X1X7X3

Horizontal Cycle Register HCR 0x

Horizontal Sync Width Register HSWR

Horizontal Border Start Register HBSR

Horizontal Display Start Register HDSR

Horizontal Dosplay End Register HDER

Horizontal Border End Register HCER

Vertical Cycle RegisterVCR

Vertical Sync Width RegisterVSWR

Vertical Border Start RegisterVBSR

Vertical Display Start Register VDSR

Vertical Display End RegisterVDER

Vertical Border End Register VBER

Mode Name Resolution Pels Color Depth 60 fps Dot Frequency + 20% sync overhead

0CGA 320x240 64K 4,8,166.635 Mhz x0 25.18 /4

1VGA 640x480 307K 4,826.54x1 28.32

2SVGA 800x600 480K 4,841.48x7 44.90

3BVGA 1024x768 786K 467.95x3 72.00

DRAM Bandwidth 155,62,62,62=341 ns341/4 = 85.25 ave access cycle time 4/85.25 = 46.9 Mbyte/sec memory bandwidth

Figure 9-1: The video and sound macrocell display format definitions

The register allocation is shown in the following table. an x denotes the actual data field, and any unused bit should be programmed with a logic zero. Do not access any register at any location other than that shown as the actual register map is multiple-mapped.

Video palette: address 0x0

all entries of the video palette are written at address 0. In order to write any or all of the palette locations, the address pointer must first be written, as described below. The palette is programmed with a 28-bit word representing the physical data field.

0000 EEEE BBBBBBBB GGGGGGGG RRRRRRRR

E=External Color ED[7:4], ED[3:0]

B=Blue Physical color

G=Green Physical color

R=Red Physical color

Video palette address pointer: address 0x1

The address pointer is programmed at address 1, and it may be programmed to any value from 0 to 255. The first write to the palette will then occur at this location, and the address pointer will post-increment so that the next palette write will occur to the following location. The counter will wrap around from 255 to 0. Once the address pointer has been written, any number of palette locations can be programmed, and the pointer can be reprogrammed at any time if only part of the whole palette is to be updated.

0001 XXXX XXXXXXXX XXXXXXXX aaaaaaaa

X=set to zero

a=PAlette address

LCD offset registers: addresses 0x30 and 0x31

These two, 8-bit registers define the offsets required for driving a dual panel LCD screen. Register 0 defines the offsets for the five and two frame duty cycle grey scales, as well as reset and test mode bits. Register 1 defines the offsets for the nine and fifteen frame duty cycle grey scales.

0011 0000 XXXXXXXX XXXXXXXX IMMM5552

X=set to zero

I = Irst, Set to 0

M=MSEL[2:0] These are test bits and should be programmed LOW.

5=Off_5 Value

2=Off_2 Value

Bits 7-4 of register 0 are only used in test mode, and must all be set to zero in normal operation.

0011 0000 XXXXXXXX XXXXXXXX FFFF 9999

X=set to zero

F= Off_15 Value

9=Off_9 Value

The registers values are dependent upon the size of the LCD screen to be driven, and are calculated in the following way:

Off_15 = (3xL + 8) mod 15

Off_9 = (7xL + 4) mod 9

Off_5 = (1xL + 3) mod 5

Off_2 = 0

Where L is the number of lines in the upper panel of the dual panel LCD screen.

Border color register: address 0x4

This register defines the physical border color, and is programmed with a 28-bit word. Note that this register is programmed directly, independent of the value of the video palette address pointer.

0100 EEEE BBBBBBBB GGGGGGGG RRRRRRRR

E=External Color ED[7:4], ED[3:0]

B=Blue Physical color

G=Green Physical color

R=Red Physical color

Cursor palette: addresses 0x5-0x7

These three registers are programmed with the physical color of the three logical cursor colors. Note that cursor logical color 00 is defined as being transparent (i.e. no cursor display), and its location is used for the Border Colour Register above.

0101 EEEE BBBBBBBB GGGGGGGG RRRRRRRR Cursor Color 1

0110 EEEE BBBBBBBB GGGGGGGG RRRRRRRR Cursor Color 2

0111 EEEE BBBBBBBB GGGGGGGG RRRRRRRR Cursor Color 3

E=External Color ED[7:4], ED[3:0]

B=Blue Physical color

G=Green Physical color

R=Red Physical color

Horizontal cycle register (HCR): address 0x80

This register defines the period, in pixels, of the horizontal scan, i.e. display time + retrace time.

This is a 14-bit register of which the bottom 2 bits must be programmed to 0. If N pixels are required in the horizontal scan period, then value (N-8) should be programmed into the HCR. (N must be a multiple of 4).

1000 0000 XXXXXXXX XXXC CCCC CCCC CC00

X=set to zero

C=Horizontal Cycle value (N-8)

Horizontal sync width register (HSWR): address 0x81

This register defines the period, in pixels, of the HSYNC pulse.

This is a 14-bit register of which the bottom bit must be programmed to 0. If N pixels are required in the HSYNC pulse, then value (N-8) should be programmed into the HSWR. (N must be a multiple of 2).

1000 0001 XXXXXXXX XXXW WWWW WWWW WWW0

X=set to zero

W=Horizontal Sync Width Value

Horizontal border start register (HBSR): address 0x82

This register defines the time, in pixels, from the start of the HSYNC pulse to the start of the border display.

This is a 14-bit register of which the bottom bit must be programmed to 0. If N pixels are required in this time, then value (N-12) should be programmed into the HBSR. (N must be a multiple of 2).

Note that this register must always be programmed, even when a border is not required. If a border is not required, then the value in the HBSR must be such as to start the border in the same place as the display start. i.e. NHBSR= NHDSR.

1000 0010 XXXXXXXX XXXB BBBB BBBB BBB0

X=set to zero

B=Horizontal Border Start Value

Horizontal display start register (HDSR): address 0x83

This register defines the time, in pixels, from the start of the HSYNC pulse to the start of the video display.

This is a 14-bit register of which the bottom bit must be programmed to 0. If N pixels are required in this time, then value (N-18) should be programmed into the HBSR. (N must be a multiple of 2).

1000 0011 XXXXXXXX XXXD DDDD DDDD DDD0

X=set to zero

D=Horizontal Display Start Value

Horizontal display end register (HDER): address 0x84

This register defines the time, in pixels, from the start of the HSYNC pulse to the end of the video display. (i.e. the first pixel which is not display).

This is a 14-bit register of which the bottom bit must be programmed to 0. If N pixels are required in this time, then value (N-18) should be programmed into the HBER. (N must be a multiple of 2)

1000 0100 XXXXXXXX XXXE EEEE EEEE EEE0

X=set to zero

E=Horizontal Display End Value

Horizontal border end register (HBER): address 0x85

This register defines the time, in pixels, from the start of the HSYNC pulse to the end of the border display. (i.e. the first pixel which is not border).

This is a 14-bit register of which the bottom bit must be programmed to 0. If N pixels are required in this time, then value (N-12) should be programmed into the HBER. (N must be a multiple of 2).

again, if no border is required, this register must still be programmed such that N HBER = NHDER.

1000 0101 XXXXXXXX XXXB BBBB BBBB BBBB0

X=set to zero

B=Horizontal Border End Value

Horizontal cursor start register (HCSR): address 0x86

This register defines the time, in pixels, from the start of the HSYNC pulse to the start of the cursor display.

This is a 14-bit register of which all bits may be programmed. If N pixels are required in this time, then value (N-17) should be programmed into the HCSR. The cursor can thus be programmed to start on any pixel. In HiRes mode, the cursor can still only be programmed to start on a normal pixel boundary. However, because the resolution of the cursor can be defined to a micro-pixel, by using different cursor images it is possible to position the cursor to any micro-pixel.

Note that only the cursor start position needs to be defined, as the cursor is automatically disabled after 32 pixels in normal mode, or 16 pixels in HiRes mode. If a cursor smaller than this is required, then the remaining bits in the cursor pattern should be programmed to logical color 00 (transparent).

1000 0110 XXXXXXXX XXXC CCCC CCCC CCCC

X=set to zero

C=Horizontal Display Start Value

Horizontal interlace register (HIR): address 0x87

address 87H is reserved. Do not attempt to program this register

.

Horizontal test registers: addresses 0x88 & 0x8H

Two registers are provided for testing the chip in production. Neither of these registers are intended to be used during normal operation of the device.

Vertical cycle register (VCR): address 0x90

This 13-bit register defines the period, in units of a RASter, of the vertical scan. i.e. display time + flyback time.

If N RASters are required in a complete frame, then value (N-2) should be programmed into the VCR.

If an interlaced display is selected, (N-3)/2 must be programmed into the VCR. [N must be odd]. Here N is still the number of RASters in a complete frame, not a field.

1001 0000 XXXXXXXX XXXC CCCC CCCC CCCC

X=set to zero

C=Vertical Cycle Value

Vertical sync width register (VSWR): address 0x91

This 13-bit register defines the width, in units of a RASter, of the VSYNC pulse.

If N RASters are required in the VSYNC pulse, then value (N - 2) should be programmed into the VSWR. The minimum value allowed for N is 2.

1001 0001 XXXXXXXX XXXW WWWW WWWW WWWW

X=set to zero

W=Vertical Sync Width Value

Vertical border start register (VBSR): address 0x92

This 13-bit register defines the time, in units of a RASter, from the start of the VSYNC pulse to the start of the border display.

If N RASters are required in this time, then value (N-1) should be programmed into the VBSR.

If no border is required, this register must still be programmed, in this CASe to the same value as the VDSR.

1001 0010 XXXXXXXX XXXB BBBB BBBB BBBB

X=set to zero

B=Vertical Border Start Value

Vertical display start register (VDSR): address 0x93

This 13-bit register defines the time, in units of a RASter, from the start of the VSYNC pulse to the start of the video display.

If N RASters are required in this time, then value (N-1) should be programmed into the VDSR.

1001 0011 XXXXXXXX XXXD DDDD DDDD DDDD

X=set to zero

D=Vertical Display Start Value

Vertical display end register (VDER): address 0x94

This 13-bit register defines the time, in units of a RASter, from the start of the VSYNC pulse to the end of the video display. (i.e. the first RASter on which the display is not present).

If N RASters are required in this time, then value (N-1) should be programmed into the VDER.

1001 0100 XXXXXXXX XXXE EEEE EEEE EEEE

X=set to zero

E=Vertical Display End Value

Vertical border end register (VBER): address 0x95

This 13-bit register defines the time, in units of a RASter, from the start of the VSYNC pulse to the end of the border display. (i.e. the first RASter on which the border is not present).

If N RASters are required in this time, then value (N-1) should be programmed into the VBER.

If no border is required, then this register must be programmed to the same value as the VDER.

1001 0000 XXXXXXXX XXXW WWWW WWWW WWWW

X=set to zero

W=Vertical Sync Width Value

Vertical cursor start register (VCSR): address 0x96

This is a 15-bit register. The lower 13 bits define the time, in units of a RASter, from the start of the VSYNC pulse to the start of the cursor display. If N RASters are required in this time, then value (N-1) should be programmed into the VCSR. The upper 2 bits are used to control the display of the cursor in duplex LCD mode. They should be programmed to zero in all other modes.

When the upper 2 bits are programmed to be 11 (split screen) the meaning of VCSR and VCER are altered as follows. The cursor is displayed in the lower half-screen only from the value of VDSR to the value of VCSR, and again in the upper half screen only from the value of VCER to the value of VDER. This allows a cursor to be positioned across the boundary of the upper and lower half screens of an LCD.

1001 0110 XXXXXXXX XSSC CCCC CCCC CCCC

X=set to zero

S=Split Screen Control 00 Normal 01 Upper Half 10 Lower Half 11 Split Screen

C=Vertical Cursor Start Value

Vertical cursor end register (VCER): address 0x97

This 13-bit register defines the time, in units of a RASter, from the start of the VSYNC pulse to the end of the cursor display. (i.e. the first RASter on which the cursor is not present).

If N RASters are required in this time, then value (N-1) should be programmed into the VCER.

1001 0111 XXXXXXXX XXXE EEEE EEEE EEEE

X=set to zero

E=Vertical Cursor End Value

Vertical test registers: addresses 0x98, 0x9a & 0x9C

Three registers are provided for testing the chip in production. None of these registers are intended to be used during normal operation of the device.

External register (ereg): address 0xC

This register contains the control bits for the external functions of video and sound macrocell. In particular it controls the DaCs, the configuration of the External Port ED[7:0], and the configuration of the sync lines.

1100 0000 XXXX XXXX VVHH 0RGD 0RGB EEEE 0CRR

X=set to zero

V=Vertical Sync Mode

H=Horizontal Sync Mode

R=Hires Mode

G=LCD Grey

D=DaC Power On

RGB=Red/Green/Blue Pedestal on

E=EREG[7:4]

C=ECLK

R=EREG

EREG[1:0] are internally mapped to drive esel[1:0] by Next7500.

EREG[7:4] are exported from the chip on ED[7:4] if EREG[1:0]=3. Refer to a11.6 External support on page 11-5.

The use of pedon[2:0] and DaC is defined in a11.7 analog outputs on page 11-11.

The uses of lcd and hrm are defined in a11.6 External support on page 11-5.

ARM7500 can export a variety of sync configurations on the pins HSYNC and VSYNC, as specified by the bits 16-17 and 18-19 respectively. For further explanation see a11.6.3 Vertical and horizontal synchronisation on page 11-11.

Frequency synthesizer register (fsynreg): address 0xD

ARM7500 is able to drive a VCO to provide a suitable input frequency for the pixel clock derived from a reference clock. This is achieved by dividing the reference clock by modulus r, and the VCO clock by modulus v, and comparing the resulting frequencies. Refer to a11.1 Pixel clock on page 11-2 for a more detailed explanation. The two moduli, r and v are each 6-bit values, and are programmed in this register.

associated with each counter are 2 test bits which should normally be programmed to 0.

Setting bit[6] forces the phase comparator HIGH, which drives PCOMP HIGH.

Setting bit[7] clears the r-modulus counter.

Setting bit[14] forces the phase comparator LOW, which drives PCOMP LOW.

Setting bit[15] clears the v-modulus counter.

To reduce power consumption, this register should be programmed with large values when the frequency synthesizer is not in use. In particular, bits [6] and [14] should not be set at the same time.

To get a modulus of r, then value (r-1) should be programmed into the fsynreg. Likewise for the v-modulus.

11011 XXX XXXXXXXX vvVV VVVV rrRR RRRR

X=set to zero

v= V Test Bits

V=Modulus V

r=R Test Bits

R=Modulus R

Control register (conreg) : address 0xE

The main control register determines the basic operation of the chip. In particular the pixel clock source, the pixel rate, the number of bits/pixel, the control of the video FIFO, and the data format are programmed. In addition there is a 4-bit test register which must be programmed to zero for normal operation.

Note

The INT bit should always be set to zero.

The pixel clock (pixclk) is selected from one of 3 sources, corresponding to the respective input pins, and the selected clock is then fed through a prescaler as defined by the 3 bits conreg[4:2]. The output of this prescaler is the actual pixel clock. SeeaChapter 11: Video Features for more detail.

The Video FIFO can be programmed to have any number of quad words loaded into it at the start of display. The value chosen should take into account the bandwidth of the display as well as the latency of the DMA subsystem. Refer to aChapter 10: Video Macrocell Interface before programming these values.

Setting the dup bit configures the display for dual-panel LCDs. This is described further in aChapter 11: Video Features .

Note that after a reset the Control Register should be the first register programmed. The Power Down bit (14) must immediately be programmed LOW. The test registers bits (16 to 19) also should be programmed LOW, as any other setting will inhibit normal operation.

1110 XXXX XXXX TTTT 0PDI 0FFF BBBR RRSS

X=set to zero

T=Test Mode (set to 0 after reset)

P=Power Down (set to 0 after reset)

D=Dual Panel LCDs

I=INT (Is Set To 0 )

F=FIFO Load Control

B=Bits per Pixel

R=Pixel Rate divider

S=Pixel Clock Source

Data control register (DCTL) : address 0xF

The horizontal display width is also defined in this register, and should be programmed to be the number of words of data in a displayed RASter. It must be programmed in most configurations of the device, as it inhibits a DMA request near the end of a RASter, when there are enough words in the video FIFO for that RASter. The request is uninhibited after the HSYNC at the start of the next RASter. When driving a dual panel LCD screen, this register must be programmed with twice the number of words in a displayed RASter. Hdis should normally be programmed to zero. If Hdis is programmed to one, the inhibition of DMA requests is disabled.

Note

Bits 19:16 MUST be set to 0001 (binary).

1111 XXXX XXXX VVBB 00E1 00DD DDDD DDDD

X=set to zero

V=VRAM mode (must be 0)

B=Bus Mode(must be 0)

E=Enable

D= Horizontal Data Display width in words (4 bytes) that are loaded into the FIFO

Stereo image register 0-7: addresses 0xa0-0xa7

These are eight, 3-bit registers which define the stereo position for the eight possible channels, as defined in Chapter 12: Sound Features . (not used in the RC7500 )

1010 0aaa XXXXXXXX XXXX XXXX XXXX XSSS

X=set to zero

a=Sound Chanel address

S=Sterio Image Value

Sound frequency register: address 0xB0

This 8-bit register specifies the byte sample rate of the sound data. It is defined in units of 1mS. See aChapter 12: Sound Features for more detail.

If a sample rate of N ms is required, then N-2 should be programmed into the SFR. N may take any value between 3 and 256.

1011 0000 XXXXXXXX XXXX XXXX CCCC CCCC

X=set to zero

C=Sound Clock Divider Value

Sound control register: address 0xB1

This is a 4-bit register which defines various control bits for the sound system.

Bit 3: SCLR This bit should always be programmed LOW.

Bit 2: SDAC When HIGH, the sound DACs are enabled. Two digital signals are also output from the chip in this mode. The first, WS_LnR, denotes whether the sound is for the left or right stereo channel. The other, SD0_MUTE, goes HIGH between samples, when the sound DaCs are being muted to allow for settling. These two signals are intended to ease the connection of external audio processing systems, but for basic operation can be ignored. Note that these two signals have different functions when the serial sound interface is in use.

Bit 1: Serial Sound This bit is used to select serial sound mode.

Bit 0: CLKSEL This bit is used to select which clock is used in the sound system.

When HIGH, the Next7500as internal 32MHz I/O reference clock is used, when LOW the optional external sound clock is used.

1011 0001 XXXXXXXX XXXX XXXX XXXX CDSK

X=set to zero

C=Sound Clear (set to 0)

D=Sound DaC Enabled ( RC7500 set to 0)

S=Select Serial Sound

K:1=Internal Clock Source (IOCLK), 0= External Clock

Special Internal Functions

JOYCON (301B040)

Registers are 8 bits wide.

REG ADDR TYPE D7 D6 D5 D4 D3 D2 D1 D0

JOYCON B040 W PU3 PU2 PU1 PU0 CAP3 CAP3 CAP3 CAP3

The JOYCON register controls the functionality of joystick port. The Joystick port cosists of a open collector clamp, a voltage comparator and a 16 bit counter operated from a 2 Mhz source. The construction of this ports allows use as a single slope a/D or as a timer from 0 to 32,768 micro-seconds. The Comparator is set with a voltage of 2.0 volts (2.2K/5.5K x 5V) . When used with a 100K Pot the and the internal .01 uf capacitor, the comparator timeout will generate approximately 510 counts at half (5oK) setting and 1020 counts at full setting in 500 micro-seconds. When used as a timer the capcitor is switched out and a 10K resistor is switched in. a typical application would be timing the echo of a sonar such as the polaroid modules used in robotic cRASh avoidance. a round trip echo would consume 2 milliseconds per foot which would be a range of 0 to 16 feet within the maximum time out of 32 milliseconds.

The JOYCON detailed bit definition is as follows:

Bit Name R/W Reset Use

7:4 PU[3:0] W X a set bit adds a 10K Ohm Pullup to the input of the individual JOYSTICK a/D circuit. This allows it to be used as the load of an electrical switch or an open collector or drain transistor. When the attached switch opens the input will rise, operating the input comparator and stopping the attached 16 bit counter. Thus, the 16 bit counter acts as an event timer.

3:0 CAP[3:] R X a set bit adds a 10 nf (.01 uf ) capacitor to the input of the JOYSTICK a/D circuit. In normal operation as a resistively controlled a/D the external pullup (0 to 100K) controls the rise time of the voltage accross this capacitor. SETLEDS (301 B060)

REG ADDR TYPE D7 D6 D5 D4 D3 D2 D1 D0

SETLEDS B060 W LED7 LED6 LED5 LED4 LED3 LED2 LED1 LED0

The SETLEDS detailed bit definition is as follows:

Bit Name R/W Reset Use

7:0 LED[7:0] W X a reset bit will light the corresponding LED in a 10 LED bargraph IC.

Internal Registers at nSIOCS2 (324 0000 ) FRQCON (324 0000)

This register controls the Video Frequency generated by the clock chip and the Turbo and Power LEDs. The serial clock and ID control for the LMC1982 audio Control chip are also generated by this register. Since this chip is in simple IO space (Selected by nSIOCS2, formally used for Acorn podules) the write data is derived from the upper word (D31:16) while the read data is normally alligned. A byte write to this space will produce the same data in every byte lane and so the write byte data will still work as expected.

REG ADDR TYPE D23 D22 D21 D20 D19 D18 D17 D16

FRQCON 0000 W TURBO POW LID LCLOCK FS3 FS2 FS1 FS0

The FRQCON detailed bit definition is as follows:

Bit Name R/W Reset Use

23 TURBO W X Turbo LED control. a 0 on this bit lights the front panel TURBO LED.

22 POW W X Power LED control. a 0 on this bit lights the front panel Power LED.

21 LID W X ID bit for the LMC1982 Audio Control Chip.

20 LCLOCK W X Serial Clock for the data shifted to/from the LMC1982 Audio Chip.

19:16 FS[3:0] W X Video Frequency Control. These bits program the CH9294 Clock chip which has a built in 14.318 Mhz oscillator and two phase lock loops for CPU clock and Video Clock.

Bits 3:0Version E Version G

0 0 0 050.35 Mhz 25.18 Mhz

0 0 0 156.65 Mhz 28.32 Mhz

0 0 1 065.00 Mhz 40.00 Mhz

0 0 1 172.00 Mhz 72.00 Mhz

0 1 0 080.00 Mhz 50.00 Mhz

0 1 0 189.80 Mhz 77.00 Mhz

0 1 1 063.00 Mhz 36.00 Mhz

0 1 1 175.00 Mhz 44.90 Mhz

1 0 0 025.18 Mhz 130.0 Mhz

1 0 0 128.32 Mhz 120.0 Mhz

1 0 1 031.50 Mhz 80.00 Mhz

1 0 1 136.00 Mhz 31.50 Mhz

1 1 0 040.00 Mhz 110.0 Mhz

1 1 0 144.90 Mhz 65.00 Mhz

1 1 1 050.00 Mhz 75.00 Mhz

1 1 1 165.00 Mhz 94.50 Mhz EXTINT (324 0000)

The EXTINT (extended Interrupt) register is used to sense the buttons on the Joystick connector , the front panel Turbo, and extend the Interrupt registers to the two serial channels in the Combo IO chip.

REG ADDR TYPE D7 D6 D5 D4 D3 D2 D1 D0

EXTINT 0000 R BUT7 BUT6 BUT5 BUT4 1 TURSW SINT1 SINT0

The EXTINT detailed bit definition is as follows:

Bit Name R/W Reset Use

7:4 BUT[7:4] R X a 0 indicates that the corresponding button on the Joystick interface is being pressed.

3 RESV R 1 Pulled Up for some later use.

2 TURSW R X Turbo Switch front panel connector. This is use for what ever the programmer desires.

1:0 SINT[1:0] R X These bits are the serial channel interrupts from the Combo chip. When a serial interrupt is received the EXTINT register is read to deturmine which interrupt is active. Then the interupt is vectored to the active channel. If bot are set then handle both channels. FREQCON (324 0000)

The EXTINT detailed bit definition is as follows:

Bit Name R/W Reset Use

7 TURBO W X Write 0 to set Pin low and light Turbo LED.

6 POWLED W X Write 0 to set Pin low and light Power LED.

5 LID W X LMC1982 - Audio Control ID pin

4 LCLOCK R X LMC1982 - Audio Controler Serial Clock

3:0 FS[3:0] R X These bits are used to set the VIDCLK input frequency. IDE Hard Disk or IDE CD ROM

IDE#1 0301 07C0 to 0301 07DC

0301 0FD8 and 03010FDC IDE#2 0301 B000 to 0301 B001C

301 B038 and 301 B03C

2 IDE interfaces are provided on the RC7500 to allow for simultaneious operation of a CD ROM and IDE Hard Disk. IDE#! is selected and controlled by the 37C665 IO Combo chip., while the IDE#2 channel is selected by the EXTIO address space. The Addresses given are offsets from the base Select locations. A common low level driver can be written that takes these base locations as function inputs. An upper level driver handles normal IDE, Extended IDE, and ATAPI command protocols.

Main Task FIle Registers

REGNameR/W Description

07C0/B000 IDDATA R/W Hard Disk Data is 16 bits wide.

07C4/B004 IDERRR IDE Error register

07C4/B004 IDPREC W IDE Precompensation Cylinder (is probably ignored)

07C8/B008 IDSCNT R/W IDE Sector Count Register

07CC/B00C IDSECT R/W IDE Starting Sector Number Register

07D0/B010 IDCYLLR/W IDE Starting Cylinder Number Low Byte

07D4/B014 IDCYLH R/W IDE Starting Cylinder Number High Byte

07D8/B018 IDRVHD R/W IDE DRIVE/ HEAD Register

07DC/B01C IDSTAT R IDE Status Register

07DC/B01C IDCOMW IDE Command Register

Miscelaneous IDE registers are at the Floppy location

REGNameR/W Description

0FD8/B038 IDASTR Hard Disk Alternate Status Register

0FD8/B038 FIXEDW Hard Disk extra control bits left out of stupid WD design

0FDC/B03C FDIRR Floppy Digital Input Register (bits 6:0)

REG ADDR TYPE D7 D6 D5 D4 D3 D2 D1 D0

IDERR 04 R BB CRC - ID - AC TK DM

IDRVHD 18 R/W - - DRV1 IDRV0 HD3 HD2 HD1 HD0

IDRCOM 1C W COM7 COM6 COM5 ICOM4 COM3 COM2 COM1 COM0

IDSTAT 1C R BSY RDY WF SC DRQ CD INDEX ERR

IDAST 38 R BSY RDY WF SC DRQ CD INDEX ERR

FIXED 38 W - - - - HS3EN IDRST IRQDIS RES

FDIR 3C R - nWG nHS3 nHS2 nHS1 nHS0 nDS1 nDS0 IDDATA 0301 07C0 or 0301 B000

The IDDATA Register is extended to 16 bits for higher speed data operations. Data is transferred by processor I/O at the appropriate time in the IO routine. 32 to 16 bit packing and unpacking is done by the processor. (Don't worry - it's still very fast!) .

IDERR 0301 07C4 or 0301 B004

The IDERR Register report simple error flags at the completion of a command.

REG ADDR TYPE D7 D6 D5 D4 D3 D2 D1 D0

IDERR 0000 R BB CRC - ID - AC TK DM

The IDERR detailed bit definition is as follows:

Bit Name R/W Reset Use

7 BB R

(Get IDE Manual!!!)

SMC37C665 Functions

The SMC37C665 Super IO chip is used on the RC7500 to provide serial and Parallel communications and interfaces. It has 2 - 8252 UARTs (with FIFOs), a 8 bit Parallel bidirectional centronics printer interface, as well as a high density Floppy controller. The IDE interface is discussed in another sectiom. 37C665 Configuration Registers [0301 0FC0 and 0301 0FC4]

The super IO chip can be configured using these ports. There are 16 internal configuration registers. Port 0FC0 is used as an address pointer while port 0FC4 is used to read or write data. The power up defaults are indicated in each register description. The 37C665 is not used in the default mode, so configuration is done on each power up or reset. This operation should be done with interrupts disabled. To program the configuration registers, the following sequence must be followed:

1. Enter Configuration mode. - 2 writes of 0x55 to port 0FC0 without any other IO write.

2. Program 37C665 Configuration registers. - Write register number into 0FC0 (0-F) and then write the value into 0FC4.

3. Leave Configuration mode. - 1 Write of 0xAA to port 0FC0.

REG DEF D7 D6 D5 D4 D3 D2 D1 D0

CR0 3B VALID OSC1 OSC0 FDCEN FDCPR RES IDEAT IDEEN

CR1 9F CGFEN CAD1 CAD0 IRQP PPMD PPPW PAD1 PAD0

CR2 DC S2PW S2EN S2AD1 S2AD0 S1PW S1EN S1AD1 S1AD0

CR3 78 ADREN IDENT MFM DOP1 DOP0 PINTR FMD2 RES

CR4 00 RES ETYPE MIDI2 MIDI1 PFDC1 PFDC0 PMD1 PMD0

CR5 00 RES EXT4 DRV0x1 DENS1 DENS0 DMA IDES FDCS

CR6 FF FDD1 FDD0 FDC1 FDC0 FDB1 FDB0 FDA1 FDA0

CR7 00 RES RES RES RES MIDP1 MIDP0 FBD1 FBD0

CR8 00 ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0

CR9 00 RES RES RES RES RES ADR10 ADR9 ADR8

CRA 00 RES RES RES RES ECPF3 ECPF2 ECPF1 ECPF0

CRB ?? RES RES RES RES RES RES RES RES

CRC ?? RES RES RES RES RES RES RES RES

CRD 66/65 0 1 1 0 0 1 1/0 0/1

CRE 01 0 0 0 0 0 0 0 1

CRF 00 RES RES RES RES RES RES RES RES

CR0

REG DEF D7 D6 D5 D4 D3 D2 D1 D0

CR0 3B VALID OSC1 OSC0 FDCEN FDCPR RES IDEAT IDEEN

This register is accessable only when in configuration mode and 0FC0 has been written to 0.

The detailed bit definition is as follows:

Bit Name Reset Use

7 VALID 0 ???

6:5 OSC1:0 01 Oscillator and Baud Rate Counter Control 0 0 Osc On, Baud Rate Generator On 0 1 Osc On and BRG On when PWRGD pin is high. 1 0 Same as 01 1 1 Osc Off, Baud Rate Generator Off

4 FDCEN 1 Floppy Disk Controller Enabled

3 FDCPR 1 Floppy Disk Controller Power On

2 RES 0 Reserved, Write as 0

1 IDEAT 1 IDE is set to AT (Westernd Digital) type

0 IDEN 1 IDE Interface Enabled (IDE2)

CR1

REG DEF D7 D6 D5 D4 D3 D2 D1 D0

CR1 9F CGFEN CAD1 CAD0 IRQP PPMD PPPW PAD1 PAD0

This register is accessable only when in configuration mode and 0FC0 has been written to 1.

The detailed bit definition is as follows:

Bit Name Reset Use

7 CGFEN 1 A 1 on this bit enable further reading and writing of configuration registers. A 0 on this bit disable reading and writing of configuration registers until a power up condition.

6:5 CAD1:0 00 COM 3,4 address (If internal serial ports are used as COM3,4)

COM3 COM4 0 0 338H 238H 0 1 3E8H 2E8H 1 0 2E8H 2E0H 1 1 220H 228H

4 IRQP 1 Sets polarity of SINT1 SINT2, FINTR, and PINTR (in RC7500 set to low) 1=Active High, Inactive low; 0=Active low, Inactive Off (High-Z)

3 PPMD 1 1=Parallel Port is in printer mode, 0=Enable ECP Modes (see CR4)

2 PPPW 1 Reserved, Write as 0

1:0 PAD1:0 11 Parallel Port Address 0 0 Disabled 0 1 3BCH 1 0 378H 1 1 278H0301 09E0 (Default)

CR2

REG DEF D7 D6 D5 D4 D3 D2 D1 D0

CR2 DC S2PW S2EN S2AD1 S2AD0 S1PW S1EN S1AD1 S1AD0

This register is accessable only when in configuration mode and 0FC0 has been written to 2.

The RC7500 is programmed to the default serial port addresses.

The detailed bit definition is as follows:

Bit Name Reset Use

7 S2PW 1 Serial Port 2 Powered.

6 S2EN 1 Serial Port 2 Enabled

5:4 S2AD1:0 01 Serial Port2 Address 0 0 COM10301 0BE0 0 1 COM20301 0FE0 1 0 COM3Refer to CR1, bits 5,6 1 1 COM4Refer to CR1, bits 5,6

3 S1PW 1 Serial Port 1 Powered

2 S1EN 1 Serial Port 1 Enabled

1:0 S1AD1:0 00 Serial Port1 Address 0 0 COM10301 0BE0 0 1 COM20301 0FE0 1 0 COM2Refer to CR1, bits 5,6 1 1 COM3Refer to CR1, bits 5,6

etc.....

  • 37C665 Serial Port 1 0301 0FE0 to 0301 0FFC 2 0301 0BE0 to 0301 0BFC

    Two UARTs are included in the the 37C665 at the above addresses in defualt mode. Each UART has a 82C550 cell with a 16 byte data FIFO for maximum performance in data transfers from the host computer. The Baud rate clock is derived from the 24MHz crystal by dividing by 13. The UART is described in detail below. For more information, see the SMC 37C665 datasheet.

    The regsters associated with the UARTs are as follows:

    REG Add TYPE D7 D6 D5 D4 D3 D2 D1 D0

    RBR F/BE0 R/O SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0

    THR F/BE0 W/O SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0

    IER F/BE4 R/W - - - - EDSSI ELSI ETBEI ERBFI

    IIRF/BE8 R/O IIR7 IIR6 - - FIFEN IID1 IID0 IPENDN

    FCR F/BE8 W/O FTL1 FTL0 - - RMODE TFCLR RFCLR FIFOEN

    LCR F/BEC R/W DLAB BREAK STICK EVPAR PAREN SBSEL WLS1 WLS0

    MCR F/BF0 R/W - - - LBACK - - RTS DTR

    LSR F/BF4 R/W ERFIFO TEMT THRE ERBRK ERFRM ERPAR EROVR RDR

    MSR F/BF8 R/W - - DSR - - - DDSR -

    SCR F/BFC R/W D7 D6 D5 D4 D3 D2 D1 D0

    DLL F/BE0 W-O DL7 DL6 DL5 DL4 DL3 DL2 DL1 DL0

    DLM F/BE4 W-O DL15 DL14 DL13 DL12 DL11 DL10 DL9 DL8

    Serial Port Data Registers (RBR, THR) (Address 0301 0F/BE0)

    Received data at the SRXD input pin is shifted into the Receiver Shift Register by the 16X clock provided from the baud rate generator. This clock is synchronized to the incoming data based on the position of the start bit. When a complete character is shifted into the Receiver Shift Register, the assembled data bits are Parallel loaded into the Receiver Buffer Data Register (RBR). The Read Data Ready (RDR) flag in the Serial Port Status Register (LSR) is set.

    FIFO (and double) buffering of the received data permits continuous reception of data without losing received data. While the Receiver Shift Register is shifting a new character into the serial channel, the Receiver Buffer Register is holding a previously received character for the CPU to read. Failure to read the data in the RBR before complete reception of the next character result in the overflow of the data in the register. The Overrun Error (EROVO) flag in the LSR register indicates the overrun condition.

    During Transmit operation, the Transmitter Holding Register holds Parallel data from the internal data bus until the Transmitter Shift Register is empty and ready to accept a new character. Data Bit 0 is the first bit transmitted. The Transmit Holding register Empty (THRE) flag in LSR reflects the current status.

    The contents of the Receive Buffer Register follows below :

    REG ADDR TYPE D7 D6 D5 D4 D3 D2 D1 D0

    RBR F/BE0 R/O RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0

    The contents of the Transmit Holding Register follows below:

    REG ADDR TYPE D7 D6 D5 D4 D3 D2 D1 D0

    THR F/BE0 W/O TD7 TD6 TD5 TD4 TD3 TD2 TD1 TD0

    Interrupt Enable Register (IER) (Address 0301 F/BE4)

    The Interrupt Enable Register is used to independently enable the four types of serial channel interrupts.

    REG ADDR TYPE D7 D6 D5 D4 D3 D2 D1 D0

    IER F/BE4 R/O - - - - EDSSI ELSI ETBEI ERBFI

    The detailed bit definition is as follows:

    Bit Name R/W Reset Use 0 ERBFI R/O 0 Enable Received Data Available Interrupt [and Timeout Interrupt in FIFO mode for Host UART only] 1 ETBEI R/O 0 Enable Transmitter Holding Reg Empty Interrupt 2 ELSI R/O 0 Enable Receiver Line Status Interrupt 3 EDSSI R/O 0 Enable Modem Status Interrupt 7:4 RESV - - Not Used

    Interrupt Identification Register (IIR) (Address 0301 F/BE8)

    The Interrupt Identification Register is a read only register used to identify the four types of serial channel interrupts.

    REG ADDR TYPE D7 D6 D5 D4 D3 D2 D1 D0

    IIRF/BE8 R/O IIR7 IIR6 - - FIFEN IID1 IID0 IPENDN

    The detailed bit definition is as follows:

    Bit Name R/W Reset Use

    0 IPENDN R/O Set to 0 if ANY Interrupt is pending.

    2:1 IID[1:0] R/O 0 Interrupt Type bits [1:0] (see table below).

    3 FIFEN R/O 0 0=16C450 Mode, 1=16C550 Mode (FIFO enabled).

    5:4 RESV - - Not Used - Always 0.

    7:6 IIR[7:6] R/O 0 FCR[0]=1 sets these two bits.

    IIR Table of Pending Interrupts

    Int ID BitsPriority

    3 2 1 0 LevelInt Flag Int SourceInt Reset Control

    X X X 1 NoneNone

    0 1 1 0 FirstRecvr Line Status OE, PE, FE, or BILSR Read

    0 1 0 0 SecondRecvd Data AvailRBR Read

    1 1 0 0* SecondFIFO Status, FIFO thresh and wait timeout RBR Read

    0 0 1 0 ThirdTHREIIR Read if THRE is the source, else THR Write

    0 0 0 0 FourthModem Status -CTS, -DSR, -RI, -RSLDMSR Read FIFO Control Register (FCR) (Address 0301 F/BE8)

    The FIFO Control Register Register is used to control the operation of the built-in data FIFOs. This register is write only.

    REG ADDR TYPE D7 D6 D5 D4 D3 D2 D1 D0

    FCR F/BE8 W/O FTL1 FTL0 - - RMODE TFCLR RFCLR FIFOEN

    Bit Name R/W Reset Use

    0 FIFOEN W/O 0 When set to 1, enables both receive and transmit FIFOs.

    1 RFCLR W/O 0 Writing a 1 to this bit clears the Receive FIFO.

    2 TFCLR W/O 0 Writing a 1 to this bit clears the Transmit FIFO.

    3 RMODE W/O 0 Changes the RXRDY and TXRDY pins from mode 0 to mode 1

    5:4 RESV - - Not Used.

    7:6 FTL[1:0] W/O 00? Receive FIFO trigger level:

    FTL1 FTL0 Trigger Level

    0 0 1 byte

    0 1 4 bytes

    1 0 8 bytes

    1 1 14 bytes

    Line Control Registers (LCR) (Address 301 F/BEC)

    The format of the characters transmitted and received are controlled by the Line Control Registers.

    REG ADDR TYPE D7 D6 D5 D4 D3 D2 D1 D0

    LCR 002C R/W DLAB BREAK STICK EVPAR PAREN SBSEL WLS1 WLS0

    The detailed bit definition is as follows:

    Bit Name R/W Reset Use

    1:0 WLS[1:0] R/W 0 Word Length Select:

    WLS1 WLS0 Length

    0 0 5 Bits

    0 1 6 Bits

    1 0 7 Bits

    1 1 8 Bits

    2 SBSEL R/W 0 Stop Bit Select. This bit specifies the number of stop bits in each transmitted character. When set to 0, one stop bit is generated. When set to 1, 1.5 stop bits stop bits are generated if 5 data bits are selected, but 2 stop bits are generated if 6, 7, or 8 data bits are selected. The receiver checks for the appropriate number of stop bits.

    3 PAREN R/W 0 PArity Enable. When set to 1, a parity bit is generated and checked.

    4 EVPAR R/W 0 PArity Select. When parity is enabled, this bit selects odd parity (0) or even parity (1).

    5 STICK R/W 0 Stick PArity. When parity is enabled, a 1 causes transmission and reception of a parity bit to be in the opposite state from that indicated by EVPAR. This allows forced parity to a known state.

    6 BREAK R/W 0 Force Break. When set to 1, the serial output (TXD ) is forced to the spacing (0) state. The break is disabled by setting this bit to 0.

    The width of the break pulse created is a function of software. As a result, the first character transmitted following a break condition might have a framing error, and should be discarded. If the following sequence is used, no erroneous or extraneous characters will be transmitted because of the break: after THRE load THR with all "0"'s, set BREAK bit in responce to the next THRE. Wait for TEMT=1, then reset BREAK when normal transmission has to be restored..

    7 DLAB R/W 0 Divisor Latch Bit. When set, addresses 020 and 024 ) access the UART clock divider latches.

    MODEM Control Register (MCR) (Address 301 F/BF0)

    The DTR pin and loop back function are controlled by the Modem Control Registers:

    REG ADDR TYPE D7 D6 D5 D4 D3 D2 D1 D0

    HMCR 0030 R/W - - - LBACK - - RTS DTR

    The detailed bit definition is as follows:

    Bit Name R/W Reset Use

    0 DTR R/W 0 Data Transmitter Ready. When set to 1, the DTR output pin is forced low.

    1 RTS R/W 0 Request to Send. When set to 1, the RTS output is forced low.

    3:2 RESV - - Reserved.

    4 LBACK R/W 0 Loopback Enable. This bit provides a local loopback feature for diagnostic testing of the serial channel. When set to 1, the Transmit Data output pin (TXD ) is set to the marking state (1), and the Receive Data input pin (RXD ) is disconnected. The output of the Transmitter is looped back into the Receiver. The handshake input pin (DSR) is disconnected. The handshake output pins (DTR) are held in their inactive state (1). In the diagnostic mode, data transmitted is immediately received. This allows the processor to verify the transmit and receive data paths of the serial channels.

    7:5 RESV - - Reserved. Line Status Registers (LSR) (Address 301 F/BF4)

    The Line Status Registers hold the current status of the UART:

    REG ADDR TYPE D7 D6 D5 D4 D3 D2 D1 D0

    HLSR 0034 R/W ERFIFO TEMT THRE ERBRK ERFRM ERPAR EROVR RDR

    ERBRK, Error flags provide the status of any error conditions detected in the receiver.

    ERFRM, During reception of the stop bit(s), the error flags are set by an error condition.

    ERPAR, The error flags are not reset by the absence of an error condition in

    ERFIFO, and the next received character.

    EROVR The flags reflect the last character only if no overrun occurred

    In the LSR the setting of status bits is inhibited during status register read operations by the CPU. If a status condition is generated during a read operation, the status bit is not set until the trailing edge of the read.

    The detailed bit definition is as follows:

    Bit Name R/W Reset Use

    0 RDR R/W 0 Receive Data Ready. This bit indicates that the Receiver Buffer Register has been loaded with a received character (including Break) and that the CPU may access this data. Reset whenever register is read.

    1 EROVR R/W 0 Receive Overrun Error. This bit indicates that the character in the Receiver Buffer Register has been overwritten by a character from the Receiver Shift Register before being read by the CPU. The first character is thereby lost. Reset whenever register is read.

    2 ERPAR R/W 0 PArity Error. This bit is set when the last character received has a parity error based on the programmed versus calculated parity. Reset whenever register is read.

    3 ERFRM R/W 0 Framing Error. This bit indicates that the last character received contained an incorrect number of stop bits. This is caused by the absence of the required stop bit or by a stop bit too short to be detected. Reset whenever register is read.

    4 ERBRK R/W 0 Break Detect Error. This bit indicates that the last character received was a break character, i.e. the received data input was held low (0) for longer than a full word transmission time (start bit + data bits + parity + stop bits). Reset whenever register is read.

    5 THRE R/W 1 Transmitter Holding Register Empty. This bit indicates that the THR register is empty and may receive another character. Reset whenever THR is written to.

    6 TEMT R/W 1Transmitter Empty. This bit is set to 1 when the Transmitter Holding Register THR and the Transmitter Shift Register are both empty. It is reset whenever HTHR/VTHR is written to, and remains low until the character is transferred out of the TXD pin.

    7 ERFIFO R/W 0FIFO Error . This bit is set to 1 if the receiver FIFO is full and another character is received. MODEM Status Register (MSR) (Address 301 F/BF8)

    The Modem Status Register holds the current status of the SDSR/VUDSR pin:

    REG ADDR TYPE D7 D6 D5 D4 D3 D2 D1 D0

    MSR 0038 R/W DCD RI DSR CTS DDCD TERI DDSR DCTS

    The detailed bit definition is as follows:

    Bit Name R/W Reset Use

    0 DCTS R-O - Delta Clear to Send

    1 DDSR R-O - Delta DSR. This bit indicates that the DSR pin has changed state since the last time it was read. Not used on this board.

    2 TERI R-O - Trailing Edge Ring Indicator. Not used on this board.

    3 DDCD R-O - Delta Data Set Ready. Not used on this board.

    4 CTS R-O - Clear To Send. Reflects status of CTS pin on Serial Interface

    5 DSR R-O - Data Set Ready. This bit always reflects the value of the DSR pin . Not used on this board.

    6 RI R-O - Ring Indicator . Not used on this board.

    7 DCD R-O - Data Carrier Detect . Not used on this board.

    Scratch Registers (SCR) (Address 301 003C)

    The Scratch Register holds the a read/write byte that affects no operations in the UART:

    REG ADDR TYPE D7 D6 D5 D4 D3 D2 D1 D0

    SCR 003C R/W D7 D6 D5 D4 D3 D2 D1 D0

    Divisor Latch Registers (DLL and DLM) (Address 301 F/BE0 and F/BE4)

    These registers control the Baud Rate Generator divisor, and are only accessible when bit 7 (DLAB) in the LCR registers are set.

    REG ADDR TYPE D7 D6 D5 D4 D3 D2 D1 D0

    DLL 0020 R/W** DL7 DL6 DL5 DL4 DL3 DL2 DL1 DL0

    DLM 0024 R/W** DL15 DL14 DL13 DL12 DL11 DL10 DL9 DL8 *accessible only when LCR[7]=1.

    The baud rate generator can uses a 1.8432 MHz input clock derived from the 24Mhz floppy clock divided by. This clock is used by both UARTs. With these frequencies, standard bit rates from 50 to 38.5K bps are available. Divisors for some popular baud rates are shown below:

    Baud Rate 1.8432 MHz 120096

    240048 960012

    19200 6

    384003 Parallel Interface (0301 09E0 to 0301 09E8)

    Register Overview

    The following registers are contained in the Parallel Port logic:

    REGADDR TYPE D7 D6 D5 D4 D3 D2 D1 D0

    PDRW09E0 W/R PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0

    PSTAT09E4 R/O -BSY -ACK PE SLCT -ERR 1 1 1

    PCON09E8 W/R 1 1 DIR ENIRQ SLIN -INIT AFD STB

    PEPPA09EC R/W Parallel EPP address Port

    PEPPD0 09F0 R/W Parallel EPP mode data port 0

    PEPPD1 09F4 R/W Parallel EPP mode data port 1

    PEPPD2 09F8 R/W Parallel EPP mode data port 2

    PEPPD3 09FC R/W Parallel EPP mode data port 3

    Parallel Data Read and Write Registers (PDRW) (Address 0301 09E0)

    A single address is used for these two registers - one for reads and one for writes. A read from PDR reflects the current state of the Printer Data Port (PRD[7:0]) pins, while a write to PDW sets the state of the Printer Data Port pins.

    REG ADDR TYPE D7 D6 D5 D4 D3 D2 D1 D0

    PDR 09E0 R/O PDI7 PDI6 PDI5 PDI4 PDI3 PDI2 PDI1 PDI0

    PDW 09E0 W/O PDO7 PDO6 PDO5 PDO4 PDO3 PDO2 PDO1 PDO0

    Parallel Status Register (PSTAT) (Address 301 09E4)

    This register senses the status of the handshake signals from the host computer:

    REGADDR TYPE D7 D6 D5 D4 D3 D2 D1 D0

    PSTAT09E4 R/O -BSY -ACK PE SLCT -ERR 1 1 1

    The detailed bit definition is as follows:

    Bit Name R/W Reset Use

    0-2 resv RAlways read as 1

    3 -ERR RStaust of ERR pin

    4 SLCT RStatus of SLCT pin

    5 PERStatus of PE pin

    6 -ACK RStatus of ACK pin

    7 -BSY RStatus of BSY pin

    Parallel Control Register (PCR) (Address 0301 09E8)

    This register controls printer status that is returned to the host computer.

    REG ADDR TYPE D7 D6 D5 D4 D3 D2 D1 D0

    PCR 09E8 R/W 1 1 DIR ENIRQ SLIN -INIT AFD STB

    The detailed bit definition is as follows:

    Bit Name R/W Reset Use

    0 -STB R/W 0 Data Strobe, 1=STB pin low

    1 -AFD R/W 0 Auto Feed, 1=AFD pin low

    2 INIT R/W 0 Initialise Printer, 1=INIT pin high

    3 SLIN R/W 0 Select In, 1=SLIN pin high

    4 ENIRQ R/W 0 Enable Interrupt, 1=Enable interrupt from the ACK signal asserted low

    5 DIRR/W 0 Direction, 1=Ouput buffers are disabled allowing PD bus to be input.

    6-7 resv

    SMC91C92 Functions

    10 Base-T Ethernet Interface (Physical 0301 B800 to 0301 B81C)

    PID3 uses the SMC91C92 to provide Ethernet communications for fast download and support of TCP/IP services for embedded operating systems. The advantqages of this part are low cost, internal RAM, and straight forward programming. Since the SMC91C92 was designed for residence on the ISa bus, it conserves scarce ISa IO space by folding its 22 16 bit registers into 4 banks of 16 registers. Bank switching is achieved through the use of the Bank Switch register which is accessable at location 5C in all banks. REG Bank0Bank1Bank2Bank3 B800 TCRCONFIG MMUMT0 B804 EPHBaSEPNR/aRR MT3 B808 RCRIa0FIFOMT4 B80C COUNT Ia2POINTER MT6 B810 MIRIa4DATA - B814 MCRGENERAL DATA - B818 RESVCONTROL INTERRUPT - B81C BANKSelect register bank - common to all banks Bank Register (address 301 B81C - all Banks)

    The bits of the Bank Register are defined as follows:

    REG ADDR TYPE D15 D14 D13 D12 D11 D10 D9 D8

    BANK 005C R/W 0 0 1 1 0 0 1 1

    REG ADDR TYPE D7 D6 D5 D4 D3 D2 D1 D0

    BANK 005C R/W X X X X X X BNK1 BNK0

    The detailed bit definition is as follows:

    Bit Name R/W Reset Use

    15:8 flag R 33 Indicates that a valid 91C92 has been found

    7:2 resv R ?? Don't Care bits

    1:0 BNK R/W 00 Bank Number 0,1,2,3 Transmit Control Register TCR (address 301 B800 - Bank 0)

    The bits of the TCRr are defined as follows:

    REG ADDR TYPE D15 D14 D13 D12 D11 D10 D9 D8

    TCR 0040 R/W X X INLP SSQT FDUP MON X NOCRC

    REG ADDR TYPE D7 D6 D5 D4 D3 D2 D1 D0

    TCR 0040 R/W PADEN X X X X FCOL LOOP TXENA

    The detailed bit definition is as follows:

    Bit Name R/W Reset Use

    15:14 resv??

    13 INLP R/W 0 Internal Loop - NRZ only, does not exercise the encoder/decoder blocks

    12 SSQT R/W 0 Stop Transmission on SQET error (Signal Quality Error Test)

    11 FDUP R/W 0 Full Duplex operation. Reciever will receive frames even which transmitting.

    10 MON R/W 0 Monitor Carrier. If set the tRASnsmitter will stop if it doesnat detect its one carrier.

    9 resv

    8 NOCRC R/W 0 No CRC will be apended to the transmit fram if this bit is set.

    7 PADEN R/W 0 When set the SMC91C92 will extend short frames to 64 bytes with zeroas.

    6:3 resv

    2 FCOL0 Force Collision. When set the transmitter will force a collision. This bit is then reset.

    1 LOOP R/W 0 THis bit will cause the transmit data to be looped back to the receiver after the encoder and back through the decoder. Collision and carier sense are ignored.

    0 TXENA R/W 0 Transmit Enable. Transmit enabled when set, disabled when clear. If this bit is cleared the current frame will complete. If an error condition causes the transmitter to stop this bit will be cleared.

    LOOP BaCK MODES

    AUI INLP LOOP FDUP LOOPS ATTRaNSMITS TO NET

    X 1 X XNRZ MaCN

    X 0 1 1ENDEC N

    1 0 0 1Cable Y

    0 0 0 110Base-T driverY

    EPH Status Register TCR (address 301 B804 - Bank 0)

    The bits of the EPH register are defined as follows:

    REG ADDR TYPE D15 D14 D13 D12 D11 D10 D9 D8

    EPH 0044 R TUND LOK ROVR CROL EDEF LCaR LCOL X

    REG ADDR TYPE D7 D6 D5 D4 D3 D2 D1 D0

    EPH 0044 R TDEF LTBR SQET 16COL LMUL MCOL SCOL TXSUC

    The detailed bit definition is as follows:

    Bit Name R/W Reset Use

    15 TUND R 0 TX Underrun. How this is set is beyond me.

    14 LOK R 0 Twisted pair link OK. Set if link pulses or network traffic is detected at least every 50ms.

    13 ROVR R 0 Receiver Overrun. Set if receive packets are not emptied from DATA buffer and/or FIFO not read. also sets RX Overrun INT, which must be separately reset.

    12 CROL R 0 a 4 bit Error Counter has rolled over. You find out which one and clear this bit by reading ECR register..

    11 EDEF R 0 Excessive deferal. Last or current TX was delayed by 1518*2 byte times..

    10 LCaR R 0 Lost transmit Carrier at the end of a preamble. Operates only when MON_CSN bit in TCR is set. Will disable TXENA in TCR.

    9 LCOL R 0 Late Collision detect. Collision detected after the 64th byte.

    8 resv R 0 ??

    7 TDEF R 0 Transmit Deferred. Carrier detected in the interframe gap. Cleared at end of Transmission.

    6 LTBR R 0 Last Transmit Frame was broadCASt. Cleared at start of next transmission.

    5 SQET R 0 Signal Quality Error Test. Heart beat detector from tranciever. If not recieved the TXENA will be reset. Cleared whe setting TXENA high.

    4 16COL R 0 16 Collisions detected for a transmit frame. The TXENA will be reset. Cleared whe setting TXENA high.

    3 LMUL R 0 Last Transmit Frame was Multicast. Cleared at start of next transmission.

    2 FCOL0 Force Collision. When set the transmitter will force a collision. This bit is then reset.

    1 SCOL R 0 Single Collision Detected. Set on any collision, cleared when TXSUC set.

    0 TXSUC R 0 Transmit Successful. Cleared at start of new TX frame or when TXENA is set high. Fatal erros that prevent this bit from being set are:

    16COL; SQET fail and SSQT set; FIFO Underrun

    LCaR and MON_CSN set; LCOL Receive Control Register RCR (address 301 B808 - Bank 0)

    The bits of the RCR are defined as follows:

    REG ADDR TYPE D15 D14 D13 D12 D11 D10 D9 D8

    RCR 0048 R/W SRST FCaR resv resv PLG1 PLG0 SCRC RXEN

    REG ADDR TYPE D7 D6 D5 D4 D3 D2 D1 D0

    RCR 0048 R/W resv resv resv resv resv aMUL PRMS RX_aBORT

    The detailed bit definition is as follows:

    Bit Name R/W Reset Use

    15 SRST R/W 0 Software activated Reset. active High. SMC91C92 configuration is not preserved and EEPROM is not read.

    14 FCaR R/W 0 Filter Carrier. Wait 12 bits before recognizing carrier. Else carrier detect is immediate.

    13:12 resv R 0

    11:10 PLG R/W 0 PLL Gain adjust.

    9 SCRC R/W 0 Strip CRC. When clear, CRC is seen after the frame in the RAM.

    8 RXEN R/W 0 Receiver Enable. If cleared current frame will complete.

    7 PADEN R/W 0 When set the SMC91C92 will extend short frames to 64 bytes with zeroas.

    6:3 resv

    2 aMUL R/W 0 accept all Multicast frames in which the first bit of the Da is 1.

    1 PRMS R/W 0 accept all frames - Promiscuous mode.

    0 RX_aBORT R/W 0 Set if the received fram was aborted due to length greater than 1532 bytes. This bit is reset by writing it low.

    Overrun data

    RX_aBORT RX_OVRN_INTError Condition 10PAcket Too Long 11Run out of memoryt during Receive Counter Register ECR (address 301 B80C - Bank 0)

    The bits of the ECR are defined as follows:

    REG ADDR TYPE D15 D14 D13 D12 D11 D10 D9 D8

    ECR 004C R EDTX EDTX EDTX EDTX DTX DTX DTX DTX

    REG ADDR TYPE D7 D6 D5 D4 D3 D2 D1 D0

    ECR 004C R MCC MCC MCC MCC SCC SCC SCC SCC

    The detailed bit definition is as follows:

    Bit Name R/W Reset Use

    15:12 EDTX R 0 Excess Deferred TRASnmissions

    11:8 FCAR R/W 0 Deferred Transmissione.

    7:4 MCC R 0 Multiple Collision Count

    3:0 SCC R 0 Single Collision Count

    Reading this register will reset the counters. The counter can intcrement once per transmitt cycle Memory Information Register MIR (address 301 B810 - Bank 0)

    The bits of the MIR are defined as follows: 0x1212 (for the SMC91C92) Memory Control Register MCR (address 301 B814 - Bank 0)

    The bits of the MIR are defined as follows:

    REG ADDR TYPE D15 D14 D13 D12 D11 D10 D9 D8

    MCR 0054 R/W X X X X X X X X

    REG ADDR TYPE D7 D6 D5 D4 D3 D2 D1 D0

    MCR 0054 R/W X X X MRT MRT MRT MRT MRT

    The detailed bit definition is as follows:

    Bit Name R/W Reset Use

    15:5 resv R 0 -

    4:0 MRT R/W 0 Memory Reserved for transmit. In MRT * 256Bytes.

    If 0 the memory allocation is completely dynamic.

    If not 0 the allocation is dynamic if the free memory exceeds the programmed value. The programmed value is allocated memory in addition the transmit memory currently in use. Configuration Register CR (address 301 B800 - Bank 1)

    The bits of the CR are defined as follows:

    REG ADDR TYPE D15 D14 D13 D12 D11 D10 D9 D8

    CR 0040 R/W X X X NWaIT X FSTP SQLC aUI_SEL

    REG ADDR TYPE D7 D6 D5 D4 D3 D2 D1 D0

    CR 0040 R/W 16BIT DLNK 1 1 0 ISEL1 ISEL2 X

    The detailed bit definition is as follows:

    Bit Name R/W Reset Use

    15:13 resv??

    12 NWaIT R/W 0 No Wait States requested from bus.

    11 resv R.

    10 FSTP R/W 0 Full Step aUI interface.

    9 SQLC R/W 0 1= squelch at 240 mv, 0=squelch at 400 mv

    8 aUI_SEL R/W 0 1=Use the aUI interface connection. 0=10Base-T

    7 16BIT R/W 0 If the EN16 pin is low this bit is forced high. THis means that all data transfers to the SMC91C92 are 16 bits wide. (this is the way it is used on the PID3)

    6 DLNK R/W 0 Disable Link test functions on the 10Base-T interface.

    5:3 bits R 0 read as 110

    2:1 ISEL R/W 0 Interrupt pin select The SMC91C92 is wired toevery bit.

    0 resv R BaseRegister BAR (address 301 B804 - Bank 1)

    The bits of the CR are defined as follows: 0x1800 for address 300hex which is what it be wired to.

    8.10 Individual address Registers IaR (address 301 B808 to 50 - Bank 1)

    address Bits 15:8 Bits 7:0

    0048address0 address1

    004Caddress2 address3

    0050address4 address5 General Purpose Register GPR (address 301 B814 - Bank 1)

    This register is intialized to 0 and is used as a way of storing data in the EEPROM. This register can also be used to program the IaR and BaSE sections of the EEPROM. The word to be read or written into is addressed as the 6 lower bits of the Pointer Register (PTR). The EEPROM select bit in the Control Register (CTR) must be set to write to the EEPROM. Control Register CTR (address 301 B818 - Bank 1)

    The bits of the CR are defined as follows:

    REG ADDR TYPE D15 D14 D13 D12 D11 D10 D9 D8

    CTR 0058 R/W X RBaD PDWN X aRLS X X X

    REG ADDR TYPE D7 D6 D5 D4 D3 D2 D1 D0

    CTR 0058 R/W LENB CREN TEEN X X ESEL RELD STORE

    The detailed bit definition is as follows:

    Bit Name R/W Reset Use

    15 resv R ??

    14 RBaD R/W 0 Receive Bad. allows reeception of packets with bad CRC. If clear, packets received with bad CRC are ignored and their memory is released.

    13 PDWN R/W 0 Set to enter power down mode. Cleared by a write to any register or by a hardware RESET.

    12 resv R ??

    11 aRLS R/W 0 auto Release. When set the tranmit memory is released at the completion of a succesful transmission (when TXSUC is set).

    10:8 resv R ??

    7 LENB R/W 0 Link Error Enable. When set enable LINK_OK bit transtions to be ORed into the EPH INT bit. Writing this bit clears interrupt.

    6 CREN R/W 0 Counter Roll over enable. When set enables the CROL bit to be ORed into the EPH_INT bit.

    5 TEEN R/W 0 Transmit Error Enable. When set is enables Transmit Error to be ORed into the EPH_INT bit. (TXENA disable conditions)

    4:3 resv R

    2 ESEL R/W 0 EEPROM SELECT. This bit allow the CPU to specify the word to be writen or read from the EEPROM. When low the IaR, BaR, and CR registers can be loaded from the EEPROM only.

    1 RELD R/W 0 RELOaD - reload the IaR, BaR, and CR registers from the EEPROM.

    0 STORE R/W 0 When set starts a store cycle for loading the EEPROM. While the store operation is running the RELD and STORE bits will be read back as 1s. MMU Command Register MMUCR (address 301 B800 - Bank 2)

    The bits of the MMUCR are defined as follows:

    REG ADDR TYPE D15 D14 D13 D12 D11 D10 D9 D8

    MMUCR 0040 R/W X X X X X X X X

    REG ADDR TYPE D7 D6 D5 D4 D3 D2 D1 D0

    MMUCR 0040 R/W COM COM COM 0 0 N2 N1 N0/BUSY

    The detailed bit definition is as follows:

    Bit Name R/W Reset Use

    15:8 resv??

    7:5 COM R/W 0 Command Value

    4:3 bits R 00

    2:0 N[2:0] W 0 allocation value. (N+1)*256 bytes for a transmit operation

    0 BUSY R 0 When set, indicates that the MMU is still processing the last command.

    A second command should not be issued untill the present one completes. Completion can be read in the Interrupt Status Register

    Commands:

    COM N[2:0] Function

    000 X NOOP No Operation

    001 N TX_ALLOCATE allocate (N+1)*256 bytes for a transmit operation. Generates a completion Code at the allocation Result Register (aRR). Can optionaly gererate an interrupt. Takes (N+2)*200ns to complete

    010 X Reset MMUFrees all allocations, clear relvent interrupts, resets packet FIFO pointers

    011 X Remove Frame from FIFO. To be issued after CPU has finnished processing current receive frame

    100 X Remove and Release receve FIFO. Like 011 but also releases all memory used by the packet at the top of the FIFO.

    101 X Release Specific PAcket. Free the memory specified in the PAcket Number Register (PNR)

    110 X Enqueue TX PAcket. This is the normal method of starting a transmission. The packet to be enqueued is taken from the PNR.

    111 X Reset TX FIFOs. This command will reset the Enqueue FIF and the completion FIFO.

    PAcket Number Register PNR (address 301 B804 - Bank 2)

    REG ADDR TYPE D15 D14 D13 D12 D11 D10 D9 D8

    ARR 0045 R FaILED 0 0 APN APN APN APN APN

    REG ADDR TYPE D7 D6 D5 D4 D3 D2 D1 D0

    PNR 0044 R/W 0 0 0 PKN PKN PKN PKN PKN

    The detailed bit definition is as follows:

    Bit Name R/W Reset Use

    15 FaILED R 1 Reset upon Succesful allocation operation. Set on reset and Reset MMU commands. In Normal operation: Run MMU command, Use the ALLOC_INT bit for polling, read the aRR for result.

    14:13 bits R 00

    12:8 APN R/W 0 allocated PAcket Number. Number associated with the last allocate request. Valid only if FaILED bit is clear.

    7:5 bits R 000

    4:0 PKN R/W 0 PAcket Number for TX Operation. Some MMU command use this number for accessing a specific packet. FIFO Ports Register FIFO (address 301 B808 - Bank 2)

    REG ADDR TYPE D15 D14 D13 D12 D11 D10 D9 D8

    FIFO 0048 R REMPT 0 0 RFN RFN RFN RFN RFN

    REG ADDR TYPE D7 D6 D5 D4 D3 D2 D1 D0

    FIFO 0048 R TEMPT 0 0 TFN TFN TFN TFN TFN

    The detailed bit definition is as follows:

    Bit Name R/W Reset Use

    15 REMPT R 0 No Receive PAckets in RX FIFO, Use the RCV_INT bit for polling.

    14:13 bits R 00

    12:8 RFN R 0 Receive FIFO PAcket Number. This is the number of the packet on the top of the receve FIFO.

    7 TEMP R 0 No Transmit packets in the TX completion FIFO. Use the TX_INT for polling.

    6:5 bits R 00

    4:0 TFN R 0 Transmit Done FIFO PAcket Number. APAcke number at the output of the tx completion FIFO. Pointer Register PTR (address 301 B80C - Bank 2)

    REG ADDR TYPE D15 D14 D13 D12 D11 D10 D9 D8

    PTR 004C R/W RCV aINC REaD X X PNTR PNTR PNTR

    REG ADDR TYPE D7 D6 D5 D4 D3 D2 D1 D0

    PTR 004C R/W PNTR PNTR PNTR PNTR PNTR PNTR PNTR PNTR

    The detailed bit definition is as follows:

    Bit Name R/W Reset Use

    15 RCV R/W 0 When set the address packet is in the receive area and uses the packet number pointer to by the RFN in the FIFO register. Whe RCV is clear the address packet is in the transmit area and refers to the packet poionted to by the PAcket number Register (PNR).

    14 AINC R/W 0 auto Increment. after every DATA read or write the pointer register is incremented (by 2 in the PID3) when this bit is set.

    13 READ R/W 0 IF the READ bit is set the DATA operation must be a read and will cause a prefetch of data from the addressed offset and packet.

    12:11 resv R ?

    10:0 PNTR R/W 0 Data Pointer. This is the ofset of thebyte in the packet pointed to in the PNR. If AINC is set the pointer will increment by 2 on each data operation. The value loaded is alway even. The Pointer register should not be loaded untill 400ns after the last data operation to complete the prefetch or write operation. Data Registers DATA (address 301 B810/04 - Bank 2)

    This register is the window into the on chip RAM. Both addresses are the same. The address of Data that is read or written to is a function of the PNR and the PTR registers. Interrupt Status/ Mask Register ISR (address 301 B818 - Bank 2)

    REG ADDR TYPE D15 D14 D13 D12 D11 D10 D9 D8

    MSK 0059 R/W X X EPIM ROVM ALM TXEM TXM RCVM

    REG ADDR TYPE D7 D6 D5 D4 D3 D2 D1 D0

    IST0058 R/RST X X EPI ROVI ALI TXEI TXI RCVI

    The detailed bit definition is as follows:

    Bit Name R/W Reset Use

    15:14 resv R ?

    13 EPM R/W 0 Ethernet Protocol Handler Interrupt Mask. Set this bit to enable EPH Interrupt.

    12 ROVM R/W 0 RX Overrun Mask

    11 ALM R/W 0 allocate Interrupt Mask

    10 TXEM R/W 0 Tramsmitter Empty Interrupt Mask

    9 TXM R/W 0 Transmitter Interrupt Mask

    8 RCVM R/W 0 RX Interrupt Mask

    7:6 resv R ?

    5 EPI R 0 Ethernet Protocol Handler detected a special condition.

    Read the EPH register to get the exact cause.

    4 ROVI R/RST 0 RX Overrun - Set when the receiver overruns due to a failed memory allocation. Write 1 here to reset

    3 ALI R/W 0 allocate Interrupt - Set when an MMU allocate command is completed. Cleared by servicing theinterrupt

    2 TXEI R/W 0 Tramsmitter Empty Interrupt - Set if the TX FIFO goes empty (no more packets queued for transmission). Clear by writing a bit into this location.

    1 TXI R/W 0 Transmitter Interrupt - Set when a packet has bee succesfully transmitted. Write a 1 here to clear the interrupt.

    0 RCVI R/W 0 RX Interrupt - Set when a packet is received. Clear by reading the FIFO ports register. Interrupt Status/ Mask Register ISR (address 301 B800/0C - Bank 3)

    AddressHigh ByteLow Byte

    0040Multicast table 1Multicast table 0

    0044Multicast table 3Multicast table 2

    0048Multicast table 5Multicast table 4

    004CMulticast table 7Multicast table 6

    The 64 bit Multicast table is used for group address filtering. The CRC of the destination address is generated and the 6 most significant bits are used to address this table. If a hash value coresponds to a set bit the packet is received. (how stupid why not use the bits directly?).

    PCF8583 Clock

    The RC7500 includes a PCF8583 Clock Calender Chip with RAM. The PCF8583 is powered from the +5 Volt board power supply (from PS8/9 or PS10) or from the on board or external backup battery. This part is read or written through the 2 wire I2C bus controlled by the IOCR Register described in section 4.1.1. Beside the readable clock and calender function the PCF8583 is connected as an alarm to the ARM7500 NEVENT1 wakeup pin. The NEVENT inputs are used to wake up the RC7500 from clock stop or CPU stop conditions. See the Philips I2C peripherals for Microcontroller handbook for more complete information.

    RC7500 ROM Monitor

    The RC7500 is shipped with a ROM monitor that provides for the functionality of the standard DEMON which connects to a host computer through the serial 9 pin COM1 port (or the Ethernet). In addition the ROM monitor can operate independently from the host and can display system information on an attached VGA monitor, controlled form a standard "AT" keyboard and PS/2 mouse interfaces. The monitor also allows memory or register contents to be modified and can run an operating system boot sequence from ether the Serial port, Floppy, or IDE hard disk. RDI (Remote Debug Interface)

    10.2 SWI calls: See ARM documentation for swi calls.

    Standard input stream: Serial Port, Ethernet, Keyboard, File, etc?

    10.3 Keyboard Control.

    Enter Sequence: (TBD)

    Monitor commands same as armsd if possible

    (what about DOS debug commands?)

    (what about Clares toolkit debug commands?)

    additions: (to be coded)

    Rolling memory and/or disassembly display; (works on disks too!) using the cursor and page keys`

    Memory contents display / modify in binary, hex, word hex, mixed (like a pc), and disassembled

    Monitor RDI serial port command/data flow

    Use external VT100 terminal on serial port

    When operating system is installed, access disk files (read, modify, and write) with commands similar to memory commands.

    DOS type disk partition tables support for multiple bootable OSes on a disk. (examine/ modify tables)

    CFG (Configure command) To configure the contents of the Battery backed RAM/ Clock

    Operating System Support.

    HELIOS

    NucleusGot another 4000 bucks?

    uC/OSGive you a good deal...Free You do the port.

    RiscBSD Real UNIX from GNU people. Free when the port is finished.

    absolute Maximum Ratings

    Stresses above those listed may cause permanent damage to the device. These are stress ratings only, functional operation of this device at these on any other conditions above those indicated in this data sheet is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.

    Condition Value Range

    ambient Operating Temperature: -10 íC to + 80 íC

    Storage Temperature: -65 íC to +150 íC

    Supply Voltage to Ground:-0.5 V to Vcc + 0.3 V

    applied Output Voltage: -0.5 V to Vcc + 0.3 V

    applied Input Voltage: -0.5 V to 7.0 V

    Power Dissipation: 1.0 W RC7500 Power Requirements

    Ta = 0 to +70íC, Vcc = 5V ▒ 5%

    ICC Supply Current - 1000 ma VCC = 5.25V

    APPENDIX A

    RC7500 Board Options

    Jumper Function PositionCPUCLK

    JP1-3 CPU CLock Frequency

    0 0 055.0 Mhz

    0 0 165.0 Mhz

    Normal Programming 0 1 070.0 Mhz

    JP3 and JP2 IN (0) 0 1 180.0 Mhz

    JP1 OUT (1)1 0 045.0 Mhz

    CPUCLK = 65MHz 1 0 140.0 Mhz

    1 0 060.0 Mhz

    1 1 150.0 Mhz

    EPROM OPTIONS

    27C080 - 8MBits4Mbytes in 4 EPROMs

    27C040 - 4 MBits2MBytes

    27C020 - 2 MBits1MByte

    27C010 - 1MBits512KBytes

    27C512 - .5MBits256KBytes

    27C256 - 256KBits128KBytes

    8MB 4MB 2MB 1MB .5MB 27C256

    JP4 Pin 3 [SA17] 1-2 1-2 1-2 1-2 1-2 2-3 1-2 = La17 2-3=VCC

    JP5 Pin 2 [SA18] 1-2 1-2 1-2 1-2 2-3 2-3 1-2 = La18 2-3=VCC

    JP6 Pin 30 [SA19] 1-2 1-2 1-2 N.U. N.U N.U. 1-2 = La19 2-3=VCC

    JP7 Pin 31 [SA20] 1-2 1-2 2-3 2-3 N.U. N.U. 1-2 = La20 2-3=VCC

    JP8Pin 1 [SA21] 1-2 2-3 2-3 2-3 N.U. N.U. 1-2 = La21 2-3=VCC

    Jumper Function Description

    JP9NPORConnected to front panel reset switch

    JP10 HDDLED Connected to IDE #2 (Hard Disk IDE)

    JP11 TURBOLED Front Panel display bit (Doesnat mean anything in particular)

    JP12 TURBOSW Front Panel Turbo switch input

    JP13 POWERLED Front Panel Power On LED

    JP14 BAT4 pin Berg, Connected to standard external battery

    JP15 AUDIOIN 4 Pin Berg, for auxillary audio input

    JP16 SPEAKER 4 Pin Berg, conneced to 5 watt per channel sterio amp.

    1=Left2,3=GND 4=Right